LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 618

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
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User manual
24.7.10.3 Configure the SCT without using states
24.7.10.4 Example
The current state can be read at any time by reading the STATE register.
To change the current state by software (that is independently of any event occurring), set
the HALT bit and write to the STATE register to change the state value. Writing to the
STATE register is only allowed when the counter is halted (the HALT_L and/or HALT_H
bits are set) and no events can occur.
The SCT can be used as standard counter/timer with external capture inputs and match
outputs without using the state logic. To operate the SCT without states, configure the
SCT as follows:
Figure 69
and EV3/4) to set/clear SCT output 0. A third match event (EV2) is used to reset the
counter regardless of the current state.
In the initial state 0, match event EV0 causes the output 0 to be set to HIGH and match
event EV1 causes output 0 to be cleared. The SCT input 0 is monitored: If the input
transitions from HIGH to LOW (EV2), the state is changed to state 1, and EV3/4 are
enabled, which create the same output but triggered by different match values. If input 0
transitions from LOW to HIGH, the associated event (EV5) causes the state to change
back to state 0. In state 0, the events EV0 and EV1 are enabled.
The example uses the following SCT configuration:
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– When the counters are stopped, both an event configured to clear the STOP bit or
– When the counter are halted, only a software write to clear the HALT bit can start
– When the counters are halted, software can set any SCT output HIGH or LOW
Write zero to the STATE register (this is the default).
Write zero to the STATELD and STATEV fields in the EVCTRL registers for each
event.
Write 0x1 to the EVSTATEMASK register of each event. This enables the event.
In effect, the event is allowed to occur in a single state which never changes while the
counter is running.
1 input
1 output
5 match registers
7 events
2 states
software writing a zero to the STOP bit can start the counter again.
the counter again. No events can occur.
directly by writing to the OUT register.
shows a simple application of the SCT using two sets of match events (EV0/1
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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