LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 421

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.7.1 Interrupt/bulk endpoint bus response matrix
20.10.8.1 Setup phase
20.10.8 Control endpoint operational model
RX-dTD is complete when:
On the successful completion of the packet(s) described by the dTD, the active bit in the
dTD will be cleared and the next pointer will be followed when the Terminate bit is clear.
When the Terminate bit is set, the device controller will flush the endpoint/direction and
cease operations for that endpoint/direction. On the unsuccessful completion of a packet
(see long packet above), the dQH will be left pointing to the dTD that was in error. In order
to recover from this error condition, the DCD must properly reinitialize the dQH by clearing
the active bit and update the nextTD pointer before attempting to re-prime the endpoint.
Remark: All packet level errors such as a missing handshake or CRC error will be retried
automatically by the device controller.
There is no required interaction with the DCD for handling such errors.
Table 351. Interrupt/bulk endpoint bus response matrix
[1]
[2]
[3]
All requests to a control endpoint begin with a setup phase followed by an optional data
phase and a required status phase. The device controller will always accept the setup
phase unless the setup lockout is engaged.
Token
type
Setup
In
Out
Ping
Invalid
•
•
•
All packets described in dTD were successfully received. Total bytes in dTD will equal
zero when this occurs.
A short packet (number of bytes < maximum packet length) was received. This is a
successful transfer completion; DCD must check Total Bytes in dTD to determine the
number of bytes that are remaining. From the total bytes remaining in the dTD, the
DCD can compute the actual bytes received.
A long packet was received (number of bytes > maximum packet size) OR (total bytes
received > total bytes specified). This is an error condition. The device controller will
discard the remaining packet, and set the Buffer Error bit in the dTD. In addition, the
endpoint will be flushed and the USBERR interrupt will become active.
BS error = Force Bit Stuff Error
NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable
length protocol then ACK.
SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is
responsive.
STALL
Ignore
STALL
STALL
STALL
Ignore
All information provided in this document is subject to legal disclaimers.
Not primed
Ignore
NAK
NAK
NAK
Ignore
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Primed
Ignore
Transmit
Receive and NYET/ACK
ACK
Ignore
Underflow
n/a
BS error
n/a
n/a
Ignore
UM10430
© NXP B.V. 2011. All rights reserved.
Overflow
n/a
n/a
NAK
n/a
Ignore
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