LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 444

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 367. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description
Table 368. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description
<Document ID>
User manual
Bit
15
23:16
31:24
Bit
0
1
2
3
Symbol
RS
RST
FS0
FS1
Symbol
FS2
ITC
-
21.6.2.2 Host mode
Value
Value
0
1
0
1
Description
Not used in device mode.
Interrupt threshold control.
The system software uses this field to set the maximum rate at which the
host/device controller will issue interrupts. ITC contains the maximum
interrupt interval measured in micro-frames. Valid values are shown below.
All other values are reserved.
0x0 = Immediate (no threshold)
0x1 = 1 micro frame.
0x2 = 2 micro frames.
0x8 = 8 micro frames.
0x10 = 16 micro frames.
0x20 = 32 micro frames.
0x40 = 64 micro frames.
Reserved
Description
Run/Stop
When this bit is set to 0, the Host Controller completes the current
transaction on the USB and then halts. The HC Halted bit in the
status register indicates when the Host Controller has finished the
transaction and has entered the stopped state. Software should not
write a one to this field unless the host controller is in the Halted state
(i.e. HCHalted in the USBSTS register is a one).
When set to a 1, the Host Controller proceeds with the execution of
the schedule. The Host Controller continues execution as long as this
bit is set to a one.
Controller reset.
Software uses this bit to reset the controller. This bit is set to zero by
the Host/Device Controller when the reset process is complete.
Software cannot terminate the reset process early by writing a zero to
this register.
This bit is set to zero by hardware when the reset process is
complete.
When software writes a one to this bit, the Host Controller resets its
internal pipelines, timers, counters, state machines etc. to their initial
value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software
should not set this bit to a one when the HCHalted bit in the USBSTS
register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.
Bit 0 of the Frame List Size bits. See
This field specifies the size of the frame list that controls which bits in
the Frame Index Register should be used for the Frame List Current
index. Note that this field is made up from USBCMD bits 15, 3, and 2.
Bit 1 of the Frame List Size bits. See
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
Table
Table 369
369.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
-
0x8
0
Reset
value
0
0
0
0
…continued
Access
-
R/W
444 of 1164
Access
R/W
R/W