LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 976

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.3.4.7 ETB SRAM configuration register
42.3.4.8 CREG6 control register
Table 921. DMA muxing register (DMAMUX, address 0x4004 311C) bit description
This register selects the interface that is used to the 16 kB block of RAM located at
address 0x2000 C000. This RAM memory block can be accessed either by the ETB or be
used as normal SRAM on the AHB bus.
Note that by default, this memory area will be accessed by the ETB.
Table 922. ETB SRAM configuration register (ETBCFG, address 0x4004 3128) bit description
This register controls various aspects of the LPC18xx:
Table 923. CREG6 control register (CREG6, address 0x4004 312C) bit description
Bit
31:30
Bit
0
31:1
Bit
2:0
3
•
•
•
Bits 2:0 control the Ethernet PHY interface. The ethernet block reads this register
during set-up, and therefore the ethernet must be reset after changing the PHY
interface.
Bits 5:4 control the input channel 7 of the combined timer inputs (see
Input channel 7 is connected to input 7 of the SCT and the CAP2 channel of timer 3.
Bits 8:6 control the input mux to the timer capture channels CAP1 and CAP2 and the
SCT (see
timer input pins or are connected to the USART receive/transmit wait signal in smart
card mode.
Symbol
ETHMODE
-
Symbol
DMAMUXCH15
Symbol
ETB
-
Figure
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
Value Description
0x0
0x4
178). These particular capture inputs can be either routed to the
Rev. 00.13 — 20 July 2011
Value
0x0
0x1
0x2
0x3
Select SRAM interface
ETB accesses SRAM at address 0x2000 C000.
AHB accesses SRAM at address 0x2000 C000.
Reserved.
Selects the Ethernet mode. Reset the ethernet
after changing the PHY interface.
All other settings are reserved.
MII
RMII
USB0 ATX override. Selects USB0 RPU usage.
Reserved.
Description
selects DMA to peripheral connection for
DMA peripheral 15:
DAC
I2S1 channel 1
Reserved
Reserved
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
Reset
value
Figure
Reset
value
0
…continued
976 of 1164
Access
R/W
-
178).
Access
R/W
R/W
Access
R/W