LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 36

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

5.1 How to read this chapter
5.2 Basic configuration
5.3 Features
5.4 General description
5.5 Pin description
<Document ID>
User manual
Remark: This chapter describes the NVIC connections of parts LPC1850/30/20/10 Rev
‘A’.
The available NVIC interrupt sources vary for different parts.
The NVIC is part of the ARM Cortex-M3 core.
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
Refer to the Cortex-M3 User Guide for details of NVIC operation.
Table 12.
Function
NMI
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UM10430
Chapter 5: LPC18xx NVIC
Rev. 00.13 — 20 July 2011
Ethernet interrupt: available on LPC1850/30.
USB0 interrupt: available on LPC1850/30/20.
USB1 interrupt: available on LPC1850/30.
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3
Tightly coupled interrupt controller provides low interrupt latency
Controls system exceptions and peripheral interrupts
On the LPC18xx, the NVIC supports 32 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt
Software interrupt generation
NVIC pin description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Direction
I
Description
External Non-Maskable Interrupt (NMI) input
© NXP B.V. 2011. All rights reserved.
User manual
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