LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1062

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.9.3 Features
42.9.4 General description
Table 991. I2S clocking and power control
The I2S bus provides a standard communication interface for digital audio applications.
The I2S bus specification defines a 3-wire serial bus, having one data, one clock, and one
word select signal. The basic I2S connection has one master, which is always the master,
and one slave. The I2S interface provides a separate transmit and receive channel, each
of which can operate as either a master or a slave.
The I2S performs serial data out via the transmit channel and serial data in via the receive
channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio
data, both for stereo and mono modes. Configuration, data access and control is
performed by a APB register set. Data streams are buffered by FIFOs with a depth of
8 words.
Clock to the I2S register interface and
I2S peripheral clock.
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For connecting the I2S receive and transmit lines to the GPDMA, use the DMAMUX
register in the CREG block (see
DMA Channel Configuration registers
See
timer and SCT inputs.
The I2S input can operate in both master and slave mode.
The I2S output can operate in both master and slave mode, independent of the I2S
input.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
Versatile clocking includes independent transmit and receive fractional rate
generators, and an ability to use a single clock input or output for a 4-wire mode.
The sampling frequency (fs) can range (in practice) from 16 to 192 kHz. (16, 22.05,
32, 44.1, 48, 96, or 192 kHz) for audio applications.
Separate Master Clock outputs for both transmit and receive channels support a clock
up to 512 times the I
Word Select period in master mode is configurable (separately for I
output).
Two 8 word (32 byte) FIFO data buffers are provided, one for transmit and one for
receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the General Purpose DMA block.
Controls include reset, stop and mute options separately for I2S input and I2S output.
Table 37
All information provided in this document is subject to legal disclaimers.
for interconnections between the I2S transmit/receive lines and the
Rev. 00.13 — 20 July 2011
2
S sampling frequency.
Table
Base clock
BASE_APB1_CLK
(Section
35) and enable the GPDMA channel in the
16.6.20).
Branch clock
CLK_APB1_I2S
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
2
S input and I
Maximum
frequency
150 MHz
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2
S