LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 959

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.2.6.1 Level configuration register
Table 904. Register overview: Event router (base address 0x4004 4000)
This register works in combination with the edge configuration register EDGE (see
Table
Table 905. Level configuration register (HILO - address 0x4004 4000) bit description
Name
CLR_EN
SET_EN
STATUS
ENABLE
CLR_STAT
SET_STAT
Bit
0
1
2
3
4
5
907) to configure the level and edge detection for each input to the event router.
Symbol
WAKEUP0_L
WAKEUP1_L
WAKEUP2_L
WAKEUP3_L
ATIMER_L
RTC_L
All information provided in this document is subject to legal disclaimers.
W
W
R
W
W
Access
R
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Level detect mode for WAKEUP0 event.
Detect LOW level if bit 0 in the EDGE register is 0. Detect
falling edge if bit 0 in the EDGE register is 1.
Detect HIGH level if bit 0 in the EDGE register is 0. Detect
rising edge if bit 0 in the EDGE register is 1.
Level detect mode for WAKEUP1 event. The
corresponding bit in the EDGE register must be 0.
Detect LOW level if bit 1 in the EDGE register is 0.
Detect HIGH level if bit 1 in the EDGE register is 0. Detect
rising edge if bit 1 in the EDGE register is 1.
Level detect mode for WAKEUP2 event.
Detect LOW level if bit 2 in the EDGE register is 0. Detect
falling edge if bit 2 in the EDGE register is 1.
Detect HIGH level if bit 2 in the EDGE register is 0. Detect
rising edge if bit 2 in the EDGE register is 1.
Level detect mode for WAKEUP3 event.
Detect LOW level if bit 3 in the EDGE register is 0. Detect
falling edge if bit 3 in the EDGE register is 1.
Detect HIGH level if bit 3 in the EDGE register is 0. Detect
rising edge if bit 3 in the EDGE register is 1.
Level detect mode for alarm timer event.
Detect LOW level if bit 4 in the EDGE register is 0. Detect
falling edge if bit 4 in the EDGE register is 1.
Detect HIGH level if bit 4 in the EDGE register is 0. Detect
rising edge if bit 4 in the EDGE register is 1.
Level detect mode for RTC event.
Detect LOW level if bit 5 in the EDGE register is 0. Detect
falling edge if bit 5 in the EDGE register is 1.
Detect HIGH level if bit 5 in the EDGE register is 0. Detect
rising edge if bit 5 in the EDGE register is 1.
Address
offset
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
Description
Event clear enable register
Event set enable register
Status register
Enable register
Clear register
Set register
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
Value
0x0
0x0
0x0
0x0
0x0
0x0
959 of 1164
Reset
value
0
0
0
0
0
0