LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 577

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 493. Color display driven with 2 2/3 pixel data
<Document ID>
User manual
Byte
0
1
2
23.7.10.1 STN displays
23.7.10.2 TFT displays
CLD[7]
P2[Green]
P5[Red]
P7[Blue]
23.7.10 STN and TFT data select
23.7.11 Interrupt generation
23.7.8 Panel clock generator
23.7.9 Timing controller
Each formatter consists of three 3-bit (RGB) shift left registers. RGB pixel data bit values
from the gray scaler are concurrently shifted into the respective registers. When enough
data is available, a byte is constructed by multiplexing the registered data to the correct bit
position to satisfy the RGB data pattern of LCD panel. The byte is transferred to the 3-byte
FIFO, which has enough space to store eight color pixels.
The output of the panel clock generator block is the panel clock, pin LCDDCLK. The panel
clock can be based on either the peripheral clock for the LCD block or the external clock
input for the LCD, pin LCDCLKIN. Whichever source is selected can be divided down in
order to produce the internal LCD clock, LCDCLK.
The panel clock generator can be programmed to output the LCD panel clock in the range
of LCDCLK/2 to LCDCLK/1025 to match the bpp data rate of the LCD panel being used.
The CLKSEL bit in the POL register determines whether the base clock used is CCLK or
the LCDCLKIN pin.
The primary function of the timing controller block is to generate the horizontal and vertical
timing panel signals. It also provides the panel bias and enable signals. These timings are
all register-programmable.
Support is provided for passive Super Twisted Nematic (STN) and active Thin Film
Transistor (TFT) LCD display types:
STN display panels require algorithmic pixel pattern generation to provide pseudo gray
scaling on monochrome displays, or color creation on color displays.
TFT display panels require the digital color value of each pixel to be applied to the display
data inputs.
Four interrupts are generated by the LCD controller, and a single combined interrupt. The
four interrupts are:
CLD[6]
P2[Red]
P4q[Blue]
P7[Green]
•
•
Master bus error interrupt.
Vertical compare interrupt.
CLD[5]
P1[Blue]
P4[Green]
P7[Red]
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
CLD[4]
P1[Green]
P4[Red]
P6[Blue]
CLD[3]
P1[Red]
P3[Blue]
P6[Green]
CLD[2]
P0[Blue]
P3[Green]
P6[Red]
Chapter 23: LPC18xx LCD
CLD[1]
P0[Green]
P3[Red]
P5[Blue]
UM10430
© NXP B.V. 2011. All rights reserved.
CLD[0]
P0[Red]
P2[Blue]
P5[Green]
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