LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 108

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Remark: In order to safely disable any of the branch clocks, use two separate writes to
the CLK_XXX_CFG register: first set the AUTO bit, and then on the next write, disable the
clock by setting the RUN bit to zero.
Table 83.
Remark: The output clock for the EMC clock divider
together with bit 16 in the CREG6 register
Table 84.
Bit
0
1
2
31:3
Bit
0
1
2
3
4
7:5
31:8
Symbol
RUN
AUTO
WAKEUP
-
Symbol
RUN
AUTO
WAKEUP
-
-
DIV
-
CCU1 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005
1100, 0x4005 1104,..., 0x4005 1A00) bit description
CCU1 branch clock configuration register (CLK_EMCDIV_CFG, addresses 0x4005
1478) bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
Value
0
1
0
1
0
1
0x0
0x1
0x2
0x3
0x4
Rev. 00.13 — 20 July 2011
Description
Run enable
Clock is disabled.
Clock is enabled.
Auto (AHB disable mechanism) enable
Auto is disabled.
Auto is enabled.
Wake-up mechanism enable
Wake-up is disabled.
Wake-up is enabled.
Reserved
Description
Run enable
Clock is disabled.
Clock is enabled.
Auto (AHB disable mechanism) enable
Auto is disabled.
Auto is enabled.
Wake-up mechanism enable
Wake-up is disabled.
Wake-up is enabled.
Reserved
Reserved
Clock divider value
No division (divide by 1).
Divide by 2.
Reserved
Reserved
Reserved
Reserved
Chapter 10: LPC18xx Clock Control Unit (CCU)
(Table
37).
(Table
84) must be configured
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
1
0
0
-
Reset
value
1
0
0
-
-
0
-
108 of 1164
Access
R/W
R/W
R/W
-
Access
R/W
R/W
R/W
-
-
R/W
-