LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 385

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 327. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description
<Document ID>
User manual
Bit
12
13
15:14 PIC1_0
19:16 PTC3_0
20
21
Symbol
PP
-
WKCN
WKDC
Value Description
-
0
1
-
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0
1
0
1
Port power control
Reserved
Port indicator control
Port indicators are off.
Undefined
Port test control
J_STATE
K_STATE
Wake on connect enable (WKCNNT_E)
Host/OTG controller requires port power control switches. This bit
represents the current setting of the switch (0=off, 1=on). When power is
not available on a port (i.e. PP equals a 0), the port is non-functional and
will not report attaches, detaches, etc.
When an over-current condition is detected on a powered port and PPC is
a one, the PP bit in each affected port may be transitioned by the host
controller driver from a one to a zero (removing power from the port).
Port power off.
Port power on.
Writing to this field effects the value of the pins USB0_IND1 and
USB0_IND0.
Amber
Green
Any value other than 0000 indicates that the port is operating in test mode.
The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the
test mode support specified in the EHCI specification. Writing the PTC field
to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into
the connected and enabled state at the selected speed. Writing the PTC
field back to TEST_MODE_DISABLE will allow the port state machines to
progress normally from that point. Values 0x8 to 0xF are reserved.
TEST_MODE_DISABLE
SE0 (host)/NAK (device)
Packet
FORCE_ENABLE_HS
FORCE_ENABLE_FS
FORCE_ENABLE_LS
This bit is 0 if PP (Port Power bit) is 0
Disables the port to wake up on device connects.
Writing this bit to a one enables the port to be sensitive to device connects
as wake-up events.
Wake on disconnect enable (WKDSCNNT_E)
This bit is 0 if PP (Port Power bit) is 0.
Disables the port to wake up on device disconnects.
Writing this bit to a one enables the port to be sensitive to device
disconnects as wake-up events.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
Reset
value
0
0
00
0000
0
0
© NXP B.V. 2011. All rights reserved.
385 of 1164
Access
R/W
-
R/W
R/W
R/W
R/W