LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 508

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.6.25 DMA Missed frame and buffer overflow counter register
22.6.26 DMA Receive interrupt watchdog timer register
22.6.27 DMA Current host transmit descriptor register
The DMA maintains two counters to track the number of missed frames during reception.
This register reports the current value of the counter. The counter is used for diagnostic
purposes. Bits[15:0] indicate missed frames due to the host buffer being unavailable.
Bits[27:17] indicate missed frames due to buffer overflow conditions (MTL and MAC) and
runt frames (good frames of less than 64 bytes) dropped by the MTL.
Table 430. DMA Missed frame and buffer overflow counter register (DMA_MFRM_BUFOF,
This register, when written with non-zero value, will enable the watchdog timer for RI (bit 6
in the DMA_STAT register).
Table 431. DMA Receive interrupt watchdog timer register (DMA_REC_INT_WDT, address
The Current Host Transmit Descriptor register points to the start address of the current
Transmit Descriptor read by the DMA.
Bit
15:0
16
27:17
28
31:29
Bit
7:0
31:8
Symbol
FMC
OC
FMA
OF
-
Symbol
RIWT
-
address 0x4001 1020) bit description
0x4001 1024) bit description
All information provided in this document is subject to legal disclaimers.
Description
Number of frames missed
Indicates the number of frames missed by the controller
due to the Host Receive Buffer being unavailable. This
counter is incremented each time the DMA discards an
incoming frame. The counter is cleared when this register
is read with .
Overflow bit for missed frame counter
Number of frames missed by the application
Indicates the number of frames missed by the application.
This counter is incremented each time the MTL asserts
the sideband signal mtl_rxoverflow_o. The counter is
cleared when this register is read with <tbd> .
Overflow bit for FIFO overflow counter
Reserved
Description
RI watchdog timeout
Indicates the number of system clock cycles multiplied by
256 for which the watchdog timer is set. The watchdog timer
gets triggered with the programmed value after the RxDMA
completes the transfer of a frame for which the RI status bit
is not set due to the setting in the corresponding descriptor
RDES1[31]. When the watch-dog timer runs out, the RI bit is
set and the timer is stopped. The watchdog timer is reset
when RI bit is set high due to automatic setting of RI as per
RDES1[31] of any received frame.
Reserved
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
0
0
0
Reset
value
0
0
Reset
value
0
0
Access
R/SS/RC
R/SS/RC
R/SS/RC
R/SS/RC
RO
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Access
R/W
RO