LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 696

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
30.7.4 Watchdog timer value register
30.7.5 Watchdog timer warning interrupt register
30.7.6 Watchdog timer window register
Table 626. Watchdog Feed register (FEED - 0x4008 0008) bit description
The WDTV register is used to read the current value of Watchdog timer counter.
When reading the value of the 24 bit counter, the lock and synchronization procedure
takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the
actual value of the timer when it's being read by the CPU.
Table 627. Watchdog Timer Value register (TV - 0x4008 000C) bit description
The WDWARNINT register determines the watchdog timer counter value that will
generate a watchdog interrupt. When the watchdog timer counter matches the value
defined by WDWARNINT, an interrupt will be generated after the subsequent WDCLK.
A match of the watchdog timer counter to WDWARNINT occurs when the bottom 10 bits
of the counter have the same value as the 10 bits of WARNINT, and the remaining upper
bits of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts
(4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If
WDWARNINT is set to 0, the interrupt will occur at the same time as the watchdog event.
Table 628. Watchdog Timer Warning Interrupt register (WARNINT - 0x4008 0014) bit
The WDWINDOW register determines the highest WDTV value allowed when a watchdog
feed is performed. If a feed valid sequence completes prior to WDTV reaching the value in
WDWINDOW, a watchdog event will occur.
WDWINDOW resets to the maximum possible WDTV value, so windowing is not in effect.
Values of WDWINDOW below 0x100 will make it impossible to ever feed the watchdog
successfully.
Bit
7:0
Bit
23:0
31:24
Bit
9:0
31:10
Symbol
Feed
Symbol
Count
-
Symbol
WDWARNINT
-
description
All information provided in this document is subject to legal disclaimers.
Description
Feed value should be 0xAA followed by 0x55.
Description
Counter timer value.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Description
Watchdog warning interrupt compare value.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Chapter 30: LPC18xx Windowed Watchdog timer (WWDT)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
NA
Reset value
NA
Reset value
0x00 00FF
NA
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