LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 877

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.10.2 Master Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(see
START condition has been transmitted, the interrupt service routine must load DAT with
the 7-bit slave address and the data direction bit (SLA+R). The SI bit in CON must then be
cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in
a Repeated START condition (state 0x10), the I
transmitter mode by loading DAT with SLA+W.
Figure
141). The transfer is initialized as in the master transmitter mode. When the
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
2
Chapter 37: LPC18xx I2C-bus interface
C block may switch to the master
UM10430
© NXP B.V. 2011. All rights reserved.
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