LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 514

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
22.8 DMA controller description
<Document ID>
User manual
22.7.3 IPC Receive checksum offload engine
In this mode, both IPv4 and IPv6 frames in the received Ethernet frames are detected and
processed for data integrity.You can enable this module by setting the bit 10 (IPC) of the
MAC configuration registe
frames by checking for value 0x0800 or 0x86DD, respectively, in the received Ethernet
frames. Type field. This identification applies to VLAN-tagged frames as well.
The Receive Checksum Offload engine calculates IPv4 header checksums and checks
that they match the received IPv4 header checksums. The result of this operation (pass or
fail) is given to the RFC module for insertion into the receive status word. The IP Header
Error bit is set for any mismatch between the indicated payload type (Ethernet Type field)
and the IP header version, or when the received frame does not have enough bytes, as
indicated by the IPv4 header.s Length field (or when fewer than 20 bytes are available in
an IPv4 or IPv6 header).
This engine also identifies a TCP, UDP, or ICMP payload in the received IP datagrams
(IPv4 or IPv6) and calculates the checksum of such payloads properly, as defined in the
TCP, UDP, or ICMP specifications. This engine includes the TCP/UDP/ICMPv6
pseudo-header bytes for checksum calculation and checks whether the received
checksum field matches the calculated value. The result of this operation is given as a
Payload Checksum Error bit in the receive status word. This status bit is also set if the
length of the TCP, UDP, or ICMP payload does not match the expected payload length
given in the IP header.
This engine bypasses the payload of fragmented IP datagrams, IP datagrams with
security features, IPv6 routing headers, and payloads other than TCP, UDP or ICMP.
The DMA has independent Transmit and Receive engines and a CSR space. The
Transmit engine transfers data from system memory to the device port (MTL), while the
Receive engine transfers data from the device port to the system memory. The controller
use descriptors to efficiently move data from source to destination with minimal Host CPU
intervention. The DMA is designed for packet-oriented data transfers such as frames in
Ethernet. The controller can be programmed to interrupt the Host CPU for situations such
as Frame Transmit and Receive transfer completion, and other normal/error conditions.
The DMA and the Host driver communicate through two data structures:
The DMA transfers data frames received by the core to the Receive Buffer in the Host
memory, and Transmit data frames from the Transmit Buffer in the Host memory.
Descriptors that reside in the Host memory act as pointers to these buffers. There are two
descriptor lists; one for reception, and one for transmission. The base address of each list
is written into DMA Registers
(either implicitly or explicitly). The last descriptor may point back to the first entry to create
a ring structure. Explicit chaining of descriptors is accomplished by setting the second
address chained in both Receive and Transmit descriptors (RDES1[24] and TDES1[24]).
The descriptor lists resides in the Host physical memory address space. Each descriptor
can point to a maximum of two buffers. This enables two buffers to be used, physically
•
•
Control and Status registers (CSR). See
Descriptor lists and data buffers. See
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
(Section
Table 425
22.6.1). The MAC receiver identifies IPv4 or IPv6
and
Section
Table
Section
22.9.
426. A descriptor list is forward linked
22.6.
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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