LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 120

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 93.
<Document ID>
User manual
Bit
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Symbol
SSP0_RST
SSP1_RST
I2S_RST
SPIFI_RST
CAN1_RST
CAN0_RST
-
-
-
-
-
-
-
-
Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description
…continued
11.4.2 RGU reset status register
The reset status register shows which source (if any) caused the last reset activation per
individual reset output of the RGU. When one (or more) inputs of the RGU caused the
Reset Output to go active (indicated by value 01), the corresponding
RESET_EXT_STATUS register can be read, see
The RESET_STATUS registers are cleared by writing 0 to each of the status bits.
Description
Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.
Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.
Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.
Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.
Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.
Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 11: LPC18xx Reset Generation Unit (RGU)
Section
11.4.4.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
-
-
-
-
-
-
-
-
120 of 1164
Access
W
W
W
W
W
W
-
-
-
-
-
-
-
-