LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 563

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
23.7 LCD controller functional description
<Document ID>
User manual
The LCD controller performs translation of pixel-coded data into the required formats and
timings to drive a variety of single or dual panel monochrome and color LCDs.
Packets of pixel coded data are fed using the AHB interface, to two independent,
programmable, 32-bit wide, DMA FIFOs that act as input data flow buffers.
The buffered pixel coded data is then unpacked using a pixel serializer.
Depending on the LCD type and mode, the unpacked data can represent:
In the case of STN displays, either a value obtained from the addressed palette location,
or the true value is passed to the gray scaling generators. The hardware-coded gray scale
algorithm logic sequences the activity of the addressed pixels over a programmed number
of frames to provide the effective display appearance.
For TFT displays, either an addressed palette value or true color value is passed directly
to the output display drivers, bypassing the gray scaling algorithmic logic.
In addition to data formatting, the LCD controller provides a set of programmable display
control signals, including:
The LCD controller generates individual interrupts for:
There is also a single combined interrupt that is asserted when any of the individual
interrupts become active.
Figure 53
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An actual true display gray or color value.
An address to a 256x16 bit wide palette RAM gray or color value.
LCD panel power enable
Pixel clock
Horizontal and vertical synchronization pulses
Display bias
Upper or lower panel DMA FIFO underflow
Base address update signification
Vertical compare
Bus error
shows a simplified block diagram of the LCD controller.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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