LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 791

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 729. Register overview: I2S1 (base address 0x400A 3000)
Table 730. I2S Digital Audio Output register (DAO - address 0x400A 2000 (I2S0) and 0x400A 3000 (I2S1)) bit
<Document ID>
User manual
Name
STATE
DMA1
DMA2
IRQ
TXRATE
RXRATE
TXBITRATE
RXBITRATE
TXMODE
RXMODE
Bit
1:0
2
3
4
5
Symbol
WORDWIDTH
MONO
STOP
RESET
WS_SEL
description
35.6.1 I2S Digital Audio Output register
Access Address
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The DAO register controls the operation of the I2S transmit channel. The function of bits in
DAO are shown in
offset
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
Value Description
0x0
0x1
0x2
0x3
When 0, the interface is in master mode. When 1, the interface is in slave
Selects the number of bytes in data as follows:
8-bit data
16-bit data
Reserved, do not use this setting
32-bit data
When 1, data is of monaural format. When 0, the data is in stereo format.
When 1, disables accesses on FIFOs, places the transmit channel in mute
mode.
When 1, asynchronously resets the transmit channel and FIFO.
mode. See
with TXMODE.
All information provided in this document is subject to legal disclaimers.
Description
I2S Status Feedback Register. Contains status information about the
I2S interface.
I2S DMA Configuration Register 1. Contains control information for
DMA request 1.
I2S DMA Configuration Register 2. Contains control information for
DMA request 2.
I2S Interrupt Request Control Register. Contains bits that control how
the I2S interrupt request is generated.
I2S Transmit MCLK divider. This register determines the I2S TX MCLK
rate by specifying the value to divide PCLK by in order to produce
MCLK.
I2S Receive MCLK divider. This register determines the I2S RX MCLK
rate by specifying the value to divide PCLK by in order to produce
MCLK.
I2S Transmit bit rate divider. This register determines the I2S transmit
bit rate by specifying the value to divide TX_MCLK by in order to
produce the transmit bit clock.
I2S Receive bit rate divider. This register determines the I2S receive bit
rate by specifying the value to divide RX_MCLK by in order to produce
the receive bit clock.
I2S Transmit mode control.
I2S Receive mode control.
Table
Section 35.7.2
Rev. 00.13 — 20 July 2011
730.
for a summary of useful combinations for this bit
Chapter 35: LPC18xx I2S interface
UM10430
© NXP B.V. 2011. All rights reserved.
791 of 1164
Reset
value
0x7
0
0
0
0
0
0
0
0
0
0
0
Reset
value
01
0
1