LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 131

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
11.4.4.1 Reset external status register 0 for CORE_RST
11.4.4.2 Reset external status register 1 for PERIPH_RST
11.4.4 Reset external status registers
The external status registers indicate which input to the reset generator caused the reset
output to go active. Any bit set to 1 in the Reset external status register should be cleared
to 0 after a read operation to allow the detection of the next reset.
All reset generators except the WWDT time-out reset, the BOD reset, the reset signal
from the PMU, and the software reset, which have no inputs, have an associated external
status register. The CORE_RST reset generator has three possible inputs (the WWDT
time-out reset, the BOD reset, and the PMU), and which input caused the reset is
indicated in the external status register. All other reset generators have only one input
which, depending on the hierarchy, can be either the CORE_RST, the
PERIPHERAL_RST, or the MASTER_RST.
Note that the external status register does not show whether or not the reset was
activated by a software reset. The software reset is indicated in the reset status registers 0
to 3 (see
This register shows whether or not any of the inputs to the CORE_RST reset generator
has activated the CORE_RST. The CORE_RST can be activated by the external reset
pin, a WWDT time-out, a BOD reset or by writing to bit 0 of the RESET_CTRL0 register.
Table 100. Reset external status register 0 (RESET_EXT_STAT0, address 0x4005 3400) bit
This register shows whether or not the CORE_RST output has activated the
PERIPH_RST. A reset generated from the CORE_RST is the only possible reset source
for the PERIPH_RST aside from a software reset by writing to the RESET_CTRL register.
Bit
0
1
2
3
4
5
31:6 -
Symbol
EXT_RESET
-
-
-
BOD_RESET
WWDT_RESET Reset activated by WWDT time-out. Write 0 to clear.
Table 94
description
All information provided in this document is subject to legal disclaimers.
to
Table
Rev. 00.13 — 20 July 2011
Description
Reset activated by external reset from reset pin.
Write 0 to clear.
0 = Reset not activated by reset pin
1 = Reset activated
Reserved. Do not modify; read as logic 0.
Reserved. Do not modify; read as logic 0.
Reserved. Do not modify; read as logic 0.
Reset activated by BOD reset. Write 0 to clear.
0 = Reset not activated by BOD
1 = Reset activated
0 = Reset not activated by WWDT
1 = Reset activated
Reserved. Do not modify; read as logic 0.
97).
Chapter 11: LPC18xx Reset Generation Unit (RGU)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
131 of 1164
Access
R/W
-
-
-
R/W
R/W
-