LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 395

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 337. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 61C0) bit description
[1]
Table 338. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to
<Document ID>
User manual
Bit
16
17
19:18 TXT1_0
22:20 -
23
31:24 -
Bit
0
There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most
systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set after
writing a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking the
associated ENDPTSETUPSTAT bit.
Symbol
TXS
-
TXE
Symbol
RXS
0x4000 61D4 (ENDPTCTRL5)) bit description
20.6.24 Endpoint 1 to 5 control registers
Value
0
1
-
-
-
Value
0
1
Each endpoint that is not a control endpoint has its own register to set the endpoint type
and enable or disable the endpoint.
Remark: The reset value for all endpoint types is the control endpoint. If one endpoint
direction is enabled and the paired endpoint of opposite direction is disabled, then the
endpoint type of the unused direction must be changed from the control type to any other
type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
for the data PID tracking on the active endpoint.
Description
Tx endpoint stall
Endpoint ok.
Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared
by hardware until the associated ENDSETUPSTAT bit is cleared.
reserved
Endpoint type
Endpoint 0 is always a control endpoint.
reserved
Tx endpoint enable
Endpoint enabled. Control endpoint 0 is always enabled. This bit is
always 1.
reserved
Description
Rx endpoint stall
Endpoint ok.
This bit will be cleared automatically upon receipt of a SETUP
request if this Endpoint is configured as a Control Endpoint and this
bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.
Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
[1]
Reset
value
00
1
Reset
value
0
UM10430
© NXP B.V. 2011. All rights reserved.
…continued
R/W
R/W
Access
RO
RO
Access
395 of 1164