LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 629

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
25.7.10 Timer external match registers
25.7.9 Timer capture registers (CR0 - CR3)
Table 541. Timer capture control registers (CCR - addresses 0x4008 4028 (TIMER0),
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Table 542. Timer capture registers CR0 to 3 (CR, address 0x4008 402C (CR0) to 0x4008 4038
The External Match Register provides both control and status of the external match pins.
In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a
Match number, 0 through 3.
Match events for Match 0 and Match 1 in each timer can cause a DMA request, see
Section
Bit
8
9
10
11
31:12 -
Bit
31:0
Symbol
CAP2I
CAP3RE
CAP3FE
CAP3I
25.7.12.
Symbol
CAP
0x4008 5020 (TIMER1), 0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3)) bit
description
(CR3) (TIMER0), 0x4008 502C (CR0) to 0x4008 5038 (CR3) (TIMER1), 0x400C 302C
(CR0) to 0x400C 3038 (CR3) (TIMER2), 0x400C 402C (CR0) to 0x400C 4038 (CR3)
(TIMER3)) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
1
0
1
0
1
0
1
0
Rev. 00.13 — 20 July 2011
…continued
Interrupt on CAPn.2 event
A CR2 load due to a CAPn.2 event will generate an interrupt.
This feature is disabled.
Capture on CAPn.3 rising edge
A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded
with the contents of TC.
This feature is disabled.
Capture on CAPn.3 falling edge
A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded
with the contents of TC.
This feature is disabled.
Interrupt on CAPn.3 event:
A CR3 load due to a CAPn.3 event will generate an interrupt.
This feature is disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Timer counter capture value.
Chapter 25: LPC18xx Timer0/1/2/3
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
Reset
value
0
0
0
0
NA