LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 547

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.6.1.1 Horizontal timing restrictions
23.6.2 Vertical Timing register
DMA requests new data at the start of a horizontal display line. Some time must be
allowed for the DMA transfer and for data to propagate down the FIFO path in the LCD
interface. The data path latency forces some restrictions on the usable minimum values
for horizontal porch width in STN mode. The minimum values are HSW = 2 and HBP = 2.
Single panel mode:
Dual panel mode:
If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10,
data does not corrupt for PCD = 4, the minimum value.
The TIMV register controls the Vertical Synchronization pulse Width (VSW), the Vertical
Front Porch (VFP) period, the Vertical Back Porch (VBP) period, and the Lines-Per-Panel
(LPP).
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HSW = 3 pixel clock cycles
HBP = 5 pixel clock cycles
HFP = 5 pixel clock cycles
Panel Clock Divisor (PCD) = 1 (LCDCLK / 3)
HSW = 3 pixel clock cycles
HBP = 5 pixel clock cycles
HFP = 5 pixel clock cycles
PCD = 5 (LCDCLK / 7)
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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