LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 433

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.11.2 Device power states
Bus powered peripheral devices are required by the USB specification to support a low
power suspend state. Self powered peripheral devices and hosts set their own power
management strategies based on their system level requirements. The clocking
architecture selected is important to consider as it determines what portions of the design
will remain active when transitioned into the low power state.
Before the system clock is suspended or set to a frequency that is below the operational
frequency of the USB-HS core, the core must be moved from the operational state to a
low power state. The power strategies designed into the USB-HS core allow for the most
challenging case, a self powered device that is clocked entirely by the transceiver clock.
A bus powered peripheral device must move through the power states as directed by the
host. Optionally autonomously directed low power states may be implemented.
In the operational state both the transceiver clock and system clocks are running.
Software can initiate a low power mode autonomously by disconnecting from the host to
go into the disconnect state. Once in this state, the software can set the Suspend bit to
Fig 42. Device power state diagram
user-defined
Suspend bit
All information provided in this document is subject to legal disclaimers.
SW sets
wakeup
Host directed
Suspend
Suspend
prepare
Resume
Rev. 00.13 — 20 July 2011
for
start
3 ms
idle
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
interrupt
received
resume
operational
Resume
Suspend bit
SW sets
(clock may be suspended)
Lock power states
Autonomous
disconnect
disconnect
Suspend
Low-power
request
UM10430
© NXP B.V. 2011. All rights reserved.
user-defined
wakeup
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