LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 228

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
14.4.3 Timer 0 CAP0_2 capture input multiplexer (CAP0_2_IN)
14.4.4 Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN)
Table 136. Timer 0 CAP0_1 capture input multiplexer (CAP0_1_IN, address 0x400C 7004) bit
Table 137. Timer 0 CAP0_2 capture input multiplexer (CAP0_2_IN, address 0x400C 7008) bit
Table 138. Timer 0 CAP0_3 capture input multiplexer (CAP0_3_IN, address 0x400C 700C) bit
Bit
31:8
Bit
0
1
2
3
7:4
31:8
Bit
0
1
2
Symbol
-
Symbol
INV
EDGE
SYNCH
Symbol
INV
EDGE
SYNCH
PULSE
SELECT
-
description
description
description
All information provided in this document is subject to legal disclaimers.
Value
0x1
0x2
Value
0
1
0
1
0
1
0
1
0x0
0x1
0x2
Value
0
1
0
1
0
Rev. 00.13 — 20 July 2011
Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA)
Description
Invert input
Not inverted.
Input inverted.
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Description
U2_TXD
T0_CAP1
Reserved
Description
Invert input
Not inverted.
Input inverted.
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0x3 to 0xF are reserved.
CTIN_2
Reserved
T0_CAP2
Reserved
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
Reset
value
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Reset
value