LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 716

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.4 UART Interrupt Enable Register
Table 666. UART Divisor Latch LSB Register when DLAB = 1 (DLL - addresses 0x4008 1000
Table 667. UART Divisor Latch MSB Register when DLAB = 1 (DLM - addresses 0x4008 1004
The IER is used to enable the four UART interrupt sources.
Table 668. UART Interrupt Enable Register when DLAB = 0 (IER - addresses 0x4008 1004
Bit
7:0
31:8 -
Bit
7:0
31:8 -
Bit
0
1
2
3
6:4
7
8
DLLSB
Symbol
Symbol
DLMSB
Symbol
RBRIE
THREIE
RXIE
-
-
-
ABEOINTEN
(UART0), 0x400C 1000 (UART2), 0x400C 2000 (UART3)) bit description
(UART0), 0x400C 1004 (UART2), 0x400C 2004 (UART3)) bit description
(UART0), 0x400C 1004 (UART2), 0x400C 2004 (UART3) ) bit description
All information provided in this document is subject to legal disclaimers.
Description
Divisor latch LSB.
The UART Divisor Latch LSB Register, along with the DLM
register, determines the baud rate of the UART.
Reserved
Description
Divisor latch MSB.
The UART Divisor Latch MSB Register, along with the DLL
register, determines the baud rate of the UART.
Reserved
Value
Rev. 00.13 — 20 July 2011
0
1
0
1
0
1
0
1
-
-
Disable the RDA interrupt.
Enable the RDA interrupt.
THRE Interrupt Enable.
Disable the THRE interrupt.
Enable the THRE interrupt.
Disable the RX line status interrupts.
Enable the RX line status interrupts.
Reserved
Reserved
Enables the end of auto-baud interrupt.
Disable end of auto-baud Interrupt.
Enable end of auto-baud Interrupt.
Description
RBR Interrupt Enable.
Enables the Receive Data Available interrupt for UART. It
also controls the Character Receive Time-out interrupt.
Enables the THRE interrupt for UART. The status of this
interrupt can be read from LSR[5].
RX Line Interrupt Enable.
Enables the UART RX line status interrupts. The status of
this interrupt can be read from LSR[4:1].
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x01
-
Reset value
0x00
-
716 of 1164
Reset
value
0
0
0
-
NA
0
0