LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 333

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.10 Dynamic Memory Last Data Out to Active Time register
19.7.9 Dynamic Memory Self Refresh Exit Time register
Table 273. Dynamic Memory Active to Precharge Command Period register (DYNAMICRAS -
The DynamicTSREX register enables you to program the self-refresh exit time, tSREX. It
is recommended that this register is modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tSREX, for devices without this parameter you use the same
value as tXSR. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 274. Dynamic Memory Self Refresh Exit Time register (DYNAMICSREX - address
The DynamicTAPR register enables you to program the last-data-out to active command
time, tAPR. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tAPR. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 275. Dynamic Memory Last Data Out to Active Time register (DYNAMICAPR - address
Bit
3:0
31:4
Bit
3:0
31:4
Bit
3:0
31:4
Symbol
tAPR
-
Symbol
tSREX
Symbol Description
tRAS
-
-
address 0x4000 5034) bit description
0x4000 5038) bit description
0x4000 503C) bit description
All information provided in this document is subject to legal disclaimers.
Active to precharge command period.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Last-data-out to active command time.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Self-refresh exit time.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
333 of 1164
Reset
value
0xF
-
Reset
value
0xF
-
Reset
value
0xF
-