LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 891

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.11.5.1 State: 0x00
37.11.5.2 Master States
37.11.5.3 State: 0x08
37.11.3 Start Master Receive function
37.11.4 I
37.11.5 Non mode specific states
Begin a Master Receive operation by setting up the buffer, pointer, and data count, then
initiating a START.
Determine the I
Bus Error. Enter not addressed Slave mode and release bus.
State 08 and State 10 are for both Master Transmit and Master Receive modes. The R/W
bit decides whether the next state is within Master Transmit mode or Master Receive
mode.
A START condition has been transmitted. The Slave Address + R/W bit will be
transmitted, an ACK bit will be received.
2
2. Set up the Slave Address to which data will be transmitted, and add the Write bit.
3. Write 0x20 to CONSET to set the STA bit.
4. Set up data to be transmitted in Master Transmit buffer.
5. Initialize the Master data counter to match the length of the message being sent.
6. Exit
1. Initialize Master data counter.
2. Set up the Slave Address to which data will be transmitted, and add the Read bit.
3. Write 0x20 to CONSET to set the STA bit.
4. Set up the Master Receive buffer.
5. Initialize the Master data counter to match the length of the message to be received.
6. Exit
1. Read the I
2. Use the status value to branch to one of 26 possible state routines.
1. Write 0x14 to CONSET to set the STO and AA bits.
2. Write 0x08 to CONCLR to clear the SI flag.
3. Exit
1. Write Slave Address with R/W bit to DAT.
2. Write 0x04 to CONSET to set the AA bit.
3. Write 0x08 to CONCLR to clear the SI flag.
4. Set up Master Transmit mode data buffer.
C interrupt routine
2
2
C status from STA.
All information provided in this document is subject to legal disclaimers.
C state and which state routine will be used to handle it.
Rev. 00.13 — 20 July 2011
Chapter 37: LPC18xx I2C-bus interface
UM10430
© NXP B.V. 2011. All rights reserved.
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