LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 286

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
16.8 Using the DMA controller
<Document ID>
User manual
16.8.1.1 Enabling the DMA controller
16.8.1.2 Disabling the DMA controller
16.8.1.3 Enabling a DMA channel
16.8.1.4 Disabling a DMA channel
16.8.1.5 Setting up a new DMA transfer
16.8.1 Programming the DMA controller
All accesses to the DMA Controller internal register must be word (32-bit) reads and
writes.
To enable the DMA controller set the Enable bit in the CONFIG register.
To disable the DMA controller:
To enable the DMA channel set the channel enable bit in the relevant DMA channel
configuration register. Note that the channel must be fully initialized before it is enabled.
A DMA channel can be disabled in three ways:
Disabling a DMA channel and losing data in the FIFO
Clear the relevant channel enable bit in the relevant channel configuration register. The
current AHB transfer (if one is in progress) completes and the channel is disabled. Any
data in the FIFO is lost.
Disabling the DMA channel without losing data in the FIFO
To set up a new DMA transfer:
If the channel is not set aside for the DMA transaction:
1. Read the ENBLDCHNS controller register and find out which channels are inactive.
2. Choose an inactive channel that has the required priority.
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Read the ENBLDCHNS register and ensure that all the DMA channels have been
disabled. If any channels are active, see Disabling a DMA channel.
Disable the DMA controller by writing 0 to the DMA Enable bit in the CONFIG register.
By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost
if this method is used.
By using the active and halt bits in conjunction with the channel enable bit.
By waiting until the transfer completes. This automatically clears the channel.
Set the halt bit in the relevant channel configuration register. This causes any future
DMA request to be ignored.
Poll the active bit in the relevant channel configuration register until it reaches 0. This
bit indicates whether there is any data in the channel that has to be transferred.
Clear the channel enable bit in the relevant channel configuration register
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
UM10430
© NXP B.V. 2011. All rights reserved.
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