LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 398

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.7.5 ATX transceiver
20.7.6 Modes of operation
20.7.7 SOF/VF indicator
20.7.8 Hardware assist
The ATX_RGEN module generates a reset signal towards the ATX fulfilling above 3
requirements, no matter how the AHB reset looks like.
The USB-OTG has a USB transceiver with UTMI+ interface. It contains the required
transceiver OTG functionality; this includes:
In general, the USB-OTG can be operating either in host mode or in device mode.
Software must put the core in the appropriate mode by setting the USBMODE.CM field
(‘11’ for host mode, ‘10’ for device mode).
The USBMODE.CM field can also be equal to ‘00’, which means that the core is in idle
mode (neither host nor device mode). This will happen after the following:
The USB-OTG generates a SOF/VF indicator signal, which can be used by user specific
external logic.
In FS mode, the SOF/VF indicator signal has a frequency equal to the frame frequency,
which is about 1 kHz. The signal is high for half of the frame period and low for the other
half of the frame period. The positive edge is aligned with the start of a frame (= SOF).
In HS mode, the SOF/VF indicator signal has a frequency equal to the virtual frame
frequency. The signal is high for half of the virtual frame period and low for the other half of
the virtual frame period. The positive edge is aligned with the start of a virtual frame (=
VF).
The length of the virtual frame is defined as: VF = microframe  2
bInterval is specified in the 4-bit programmable BINTERVAL.BINT register field. The
minimum value of bInterval is 0, the maximum value is 15.
In suspend mode the SOF/VF indicator signal is turned off (= remains low).
The hardware assist provides automated response and sequencing that may not be
possible in software if there are significant interrupt latency response times. The use of
this additional circuitry is optional and can be used to assist the following three state
transitions by setting the appropriate bits in the OTGSC register:
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•
•
•
•
VBUS sensing for producing the session-valid and VBUS-valid signals.
sampling of the USB_ID input for detection of A-device or B-device connection.
charging and discharging of VBUS for starting and ending a session as B-device.
a hardware reset.
a software reset via the USBCMD.RST bit; e.g. when switching from host mode to
device mode as part of the HNP protocol (or vice versa), software must issue a
software reset by which the core will be to the idle state; this will happen in a time
frame dependent on the software.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
bInterval
UM10430
© NXP B.V. 2011. All rights reserved.
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