LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 595

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 501. SCT control register (CTRL - address 0x4000 0004) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
12:5
15:13
16
17
18
19
20
28:21
31:29
Symbol
DOWN_L
STOP_L
HALT_L
CLRCTR_L -
BIDIR_L
PRE_L
-
DOWN_H
STOP_H
HALT_H
CLRCTR_H -
BIDIR_H
PRE_H
-
24.6.3 SCT limit register
Value Description
-
-
-
0
1
-
-
-
-
0
1
-
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
This bit is 1 when the L or unified counter is counting down. It is set by hardware
when the counter’s limit is reached and BIDIR is 1. It is cleared by hardware when
the counter reaches 0.
When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events
related to the counter can occur. If such an event matches the mask in the Start
register, this bit is cleared and counting resumes.
When this bit is 1, the L or unified counter does not run and no events can occur.
This bit is set by reset.
Remark: Once set, this bit can only be cleared by software to restore counter
operation.
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
L or unified counter direction select
The counter counts up to its limit condition, then is cleared to zero.
The counter counts up to its limit, then counts down to 0.
Specifies the factor by which the SCT clock is prescaled to produce the L or unified
counter clock. The counter clock will be clocked at the rate of the SCT clock divided
by PRE_L+1.
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
Reserved
This bit is 1 when the H counter is counting down. It is set by hardware when the
counter’s limit is reached and BIDIR is 1. It is cleared by hardware when the counter
reaches 0.
When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to
the counter can occur. If such an event matches the mask in the Start register, this bit
is cleared and counting resumes.
When this bit is 1, the H counter does not run and no events can occur. This bit is set
by reset.
Remark: Once set, this bit can only be cleared by software to restore counter
operation.
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
Direction select
The H counter counts up to its limit condition, then is cleared to zero.
The H counter counts up to its limit, then counts down to 0.
Specifies the factor by which the SCT clock is prescaled to produce the H counter
clock. The counter clock will be clocked at the rate of the SCT clock divided by
PRELH+1.
Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
595 of 1164
Reset
value
0
0
1
0
0
0
0
0
1
0
0
0