LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 248

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
15.5 Register description
<Document ID>
User manual
The GPIO consists of the following blocks:
Note: In all GPIO registers, bits that are not shown are reserved.
Table 167. Register overview: GPIO pin interrupts (base address: 0x4008 7000)
Table 168. Register overview: GPIO GROUP0 interrupt (base address 0x4008 8000)
Name
ISEL
IENR
SIENR
CIENR
IENF
SIENF
CIENF
RISE
FALL
IST
Name
CTRL
PORT_POL0
PORT_POL1
PORT_POL2
•
•
•
•
The GPIO pin interrupts block at address 0x4008 7000. Registers in this block enable
the up to 8 pin interrupts selected in (see <tbd>) and configure the level and edge
sensitivity for each selected pin interrupt. The GPIO interrupt registers are listed in
<tbd> and <tbd>
The GPIO GROUP0 interrupt block at address 0x4008 8000. Registers in this block
allow to configure any pin on port 0 and 1 to contribute to a combined interrupt. The
GPIO GROUP0 registers are listed in
The GPIO GROUP1 interrupt block at address 0x4008 9000. Registers in this block
allow to configure any pin on port 0 and 1 to contribute to a combined interrupt. The
GPIO GROUP1 registers are listed in
The GPIO port block at address 0x400F 4000. Registers in this block allow to read
and write to port pins and configure port pins as inputs or outputs.The GPIO port
registers are listed in
Access Address
R/W
R/W
WO
WO
R/W
WO
WO
R/W
R/W
R/W
Access Address
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
Rev. 00.13 — 20 July 2011
offset
0x000
0x020
0x024
0x028
Table 170
Description
GPIO grouped interrupt control register
GPIO grouped interrupt port 0 polarity register
GPIO grouped interrupt port 1 polarity register
GPIO grouped interrupt port 2 polarity register
and
Section
Description
Pin Interrupt Mode register
Pin Interrupt Enable (Rising) register
Set Pin Interrupt Enable (Rising) register
Clear Pin Interrupt Enable (Rising) register
Pin Interrupt Enable Falling Edge / Active
Level register
Set Pin Interrupt Enable Falling Edge /
Active Level register
Clear Pin Interrupt Enable Falling Edge /
Active Level address
Pin Interrupt Rising Edge register
Pin Interrupt Falling Edge register
Pin Interrupt Status register
Table 168
Table 169
15.5.3.
and
and
Section
Section
Chapter 15: LPC18xx GPIO
15.5.2.
15.5.2.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0xFFFF
FFFF
0xFFFF
FFFF
0xFFFF
FFFF
248 of 1164
Reset
value
0
0
NA
NA
0
NA
NA
0
0
0