LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1139

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 858. ISP Read device serial number command. . .922
Table 859. ISP Compare command. . . . . . . . . . . . . . . . .923
Table 860. ISP Return Codes Summary . . . . . . . . . . . . .923
Table 861. IAP Command Summary . . . . . . . . . . . . . . . .926
Table 862. IAP Prepare sector(s) for write operation
Table 863. IAP Copy RAM to Flash command . . . . . . . .927
Table 864. IAP Erase Sector(s) command . . . . . . . . . . .928
Table 865. IAP Blank check sector(s) command . . . . . . .928
Table 866. IAP Read part identification number command . .
Table 867. IAP Read Boot Code version number command .
Table 868. IAP Read device serial number command. . .929
Table 869. IAP Compare command. . . . . . . . . . . . . . . . .929
Table 870. Re-invoke ISP . . . . . . . . . . . . . . . . . . . . . . . .930
Table 871. IAP Status Codes Summary . . . . . . . . . . . . .930
Table 872. Register overview: FMC (base address 0x4008
Table 873. Flash Module Signature Start register
Table 874. Flash Module Signature Stop register (FMSSTOP
Table 875. FMSW0 register bit description (FMSW0,
Table 876. FMSW1 register bit description (FMSW1,
Table 877. FMSW2 register bit description (FMSW2,
Table 878. FMSW3 register bit description (FMSW3,
Table 879. Flash module Status register (FMSTAT - 0x4008
Table 880. Flash Module Status Clear register (FMSTATCLR
Table 881. JTAG pin description . . . . . . . . . . . . . . . . . . .936
Table 882. Serial Wire Debug pin description . . . . . . . . .936
Table 883. Parallel Trace pin description. . . . . . . . . . . . .936
Table 884. NVIC pin description . . . . . . . . . . . . . . . . . . .938
Table 885. Connection of interrupt sources to the NVIC .939
Table 886. Register overview: NVIC (base address 0xE000
Table 887. Interrupt Set-Enable Register 0 register (ISER0 -
Table 888. Interrupt Clear-Enable Register 0 (ICER0 -
Table 889. Interrupt Set-Pending Register 0 register (ISPR0
Table 890. Interrupt Clear-Pending Register 0 register
Table 891. Interrupt Active Bit Register 0 (IABR0 - address
Table 892. Interrupt Priority Register 0 (IPR0 - address
Table 893. Interrupt Priority Register 1 (IPR1 - address
<Document ID>
User manual
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .927
928
929
4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .931
(FMSSTART - 0x4008 4020) bit description . .932
- 0x4008 4024) bit description . . . . . . . . . . . .932
address: 0x4008 402C) . . . . . . . . . . . . . . . . .932
address: 0x4008 4030) . . . . . . . . . . . . . . . . .932
address: 0x4008 4034) . . . . . . . . . . . . . . . . .933
address: 0x4008 4038) . . . . . . . . . . . . . . . . .933
4FE0) bit description. . . . . . . . . . . . . . . . . . . .933
- 0x0x4008 4FE8) bit description . . . . . . . . . .933
E000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .941
address 0xE000 E100) bit description . . . . .942
address 0xE000 E180) bit description . . . . .944
- address 0xE000 E200) bit description . . . .947
(ICPR0 - address 0xE000 E280) bit description .
949
0xE000 E300) bit description . . . . . . . . . . . .951
0xE000 E400) bit description . . . . . . . . . . . . .953
0xE000 E404) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .953
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 894. Interrupt Priority Register 2 (IPR2 - address
Table 895. Interrupt Priority Register 3 (IPR3 - address
Table 896. Interrupt Priority Register 4 (IPR4 - address
Table 897. Interrupt Priority Register 5 (IPR5 - address
Table 898. Interrupt Priority Register 6 (IPR6 - address
Table 899. Interrupt Priority Register 7 (IPR7 - address
Table 900. Software Trigger Interrupt Register (STIR -
Table 901. Event router clocking and power control . . . . 957
Table 902. Event router inputs . . . . . . . . . . . . . . . . . . . . 958
Table 903. Event router pin description . . . . . . . . . . . . . 958
Table 904. Register overview: Event router (base address
Table 905. Level configuration register (HILO - address
Table 906. EDGE and HILO combined register settings. 961
Table 907. Edge configuration register (EDGE - address
Table 908. Interrupt clear enable register (CLR_EN -
Table 909. Event set enable register (SET_EN - address
Table 910. Interrupt status register (STATUS - address
Table 911. Event enable register (ENABLE - address 0x4004
Table 912. Interrupt clear status register (CLR_STAT -
Table 913. Interrupt set status register (SET_STAT - address
Table 914. CREG clocking and power control . . . . . . . . 970
Table 915. Register overview: Configuration registers (base
Table 916. IRC trim register (IRCTRM, address 0x4004
Table 917. CREG0 register (CREG0, address 0x4004 3004)
Table 918. Power mode control register (PMUCON, address
Table 919. Memory mapping register (M3MEMMAP, address
Table 920. CREG5 control register (CREG5, address
Table 921. DMA muxing register (DMAMUX, address
Table 922. ETB SRAM configuration register (ETBCFG,
Table 923. CREG6 control register (CREG6, address
0xE000 E408) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
0xE000 E40C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 954
0xE000 E410) bit description . . . . . . . . . . . . . 955
0xE000 E414) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 955
0xE000 E418) bit description . . . . . . . . . . . . 955
0xE000 E41C) bit description . . . . . . . . . . . . 956
address 0xE000 EF00) bit description . . . . . 956
0x4004 4000) . . . . . . . . . . . . . . . . . . . . . . . . . 958
0x4004 4000) bit description . . . . . . . . . . . . 959
0x4004 4004) bit description . . . . . . . . . . . . 961
address 0x4004 4FD8) bit description . . . . . . 964
0x4004 4FDC) bit description . . . . . . . . . . . . 965
0x4004 4FE0) bit description . . . . . . . . . . . . . 966
4FE4) bit description . . . . . . . . . . . . . . . . . . . 967
address 0x4004 4FE8) bit description . . . . . . 968
0x4004 4FEC) bit description. . . . . . . . . . . . . 969
address 0x4004 3000) . . . . . . . . . . . . . . . . . . 971
3000) bit description . . . . . . . . . . . . . . . . . . . 971
bit description . . . . . . . . . . . . . . . . . . . . . . . . 972
0x4004 3008) bit description . . . . . . . . . . . . 972
0x4004 3100) bit description . . . . . . . . . . . . 973
0x4004 3118) bit description . . . . . . . . . . . . 973
0x4004 311C) bit description . . . . . . . . . . . . 973
address 0x4004 3128) bit description . . . . . 976
0x4004 312C) bit description . . . . . . . . . . . . 976
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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