LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 596

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.4 SCT halt condition register
24.6.5 SCT stop condition register
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
LIMIT_L (address 0x4000 4008) and LIMIT_H (address 0x4000 400A). Both the L and H
registers can be read or written in a single 32-bit read or write operation, or they can be
read or written individually.
The bits in this register set which events act as counter limits. When a limit event occurs,
the counter is cleared to zero in unidirectional mode or begins counting down in
bidirectional mode. When the counter reaches all ones, this state is always treated as a
limit event, and the counter is cleared in unidirectional mode or, in bidirectional mode,
begins counting down on the next clock edge - even if no limit event as defined by the
SCT limit register has occurred.
Table 502. SCT limit register (LIMIT - address 0x4000 0008) bit description
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
HALT_L (address 0x4000 400C) and HALT_H (address 0x4000 400E). Both the L and H
registers can be read or written in a single 32-bit read or write operation, or they can be
read or written individually.
Remark: Any event halting the counter disables its operation until software clears the
HALT bit (or bits) in the CTRL register
Table 503. SCT halt condition register (HALT - address 0x4000 000C) bit description
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STOPT_L (address 0x4000 4010) and STOP_H (address 0x4000 4012). Both the L and H
registers can be read or written in a single 32-bit read or write operation, or they can be
read or written individually.
Bit
15:0
31:16
Bit
15:0
31:16 HALTMSK_H
Symbol
HALTMSK_L
Symbol
LIMMSK_L
LIMMSK_H
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
If bit n is one, event n sets the HALT_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
If bit n is one, event n sets the HALT_H bit in the CTRL register
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
Description
If bit n is one, event n is used as a counter limit for the L or
unified counter (event 0 = bit 0, event 1 = bit 1, event 15 =
bit 15).
If bit n is one, event n is used as a counter limit for the H
counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit
31).
Chapter 24: LPC18xx State Configurable Timer (SCT)
(Table
501).
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
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0
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0