LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 392

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 333. USB Endpoint Prime register (ENDPTPRIME - address 0x4000 61B0) bit description
Table 334. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description
<Document ID>
User manual
Bit
5:0
15:6
21:16 PETB
31:22 -
Bit
5:0
Symbol
PERB
-
Symbol
FERB
20.6.20 USB Endpoint Flush register (ENDPTFLUSH)
Description
Prime endpoint receive buffer for physical OUT endpoints 5 to 0.
For each OUT endpoint, a corresponding bit is set to 1 by software to request a
buffer be prepared for a receive operation for when a USB host initiates a USB
OUT transaction. Software should write a one to the corresponding bit
whenever posting a new transfer descriptor to an endpoint. Hardware will
automatically use this bit to begin parsing for a new transfer descriptor from the
queue head and prepare a receive buffer. Hardware will clear this bit when the
associated endpoint(s) is (are) successfully primed.
PERB0 = endpoint 0
...
PERB5 = endpoint 5
reserved
Prime endpoint transmit buffer for physical IN endpoints 5 to 0.
For each IN endpoint a corresponding bit is set to one by software to request a
buffer be prepared for a transmit operation in order to respond to a USB
IN/INTERRUPT transaction. Software should write a one to the corresponding
bit when posting a new transfer descriptor to an endpoint. Hardware will
automatically use this bit to begin parsing for a new transfer descriptor from the
queue head and prepare a transmit buffer. Hardware will clear this bit when the
associated endpoint(s) is (are) successfully primed.
PETB0 = endpoint 0
...
PETB5 = endpoint 5
reserved
Description
Flush endpoint receive buffer for physical OUT endpoints 5 to 0.
Writing a one to a bit(s) will clear any primed buffers.
FERB0 = endpoint 0
...
FERB5 = endpoint 5
Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any
primed buffers. If a packet is in progress for one of the associated endpoints, then that
transfer will continue until completion. Hardware will clear this register after the endpoint
flush operation is successful.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Reset
value
0
Reset
value
0
-
0
-
UM10430
© NXP B.V. 2011. All rights reserved.
Access
R/WS
Access
R/WS
-
R/WS
-
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