LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 719

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.6 UART FIFO Control Register
[1]
[2]
[3]
[4]
The UART THRE interrupt (IIR[3:1] = 001) is a third level interrupt and is activated when
the UART THR FIFO is empty provided certain initialization conditions have been met.
These initialization conditions are intended to give the UART THR FIFO a chance to fill up
with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to THR
without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the
UART THR FIFO has held two or more characters at one time and currently, the THR is
empty. The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs
and the THRE is the highest interrupt (IIR[3:1] = 001).
The FCR controls the operation of the UART RX and TX FIFOs.
Table 671. UART FIFO Control Register Write Only (FCR - addresses 0x4008 1008 (UART0),
Bit
0
1
2
3
5:4
Values 0000, 0011, 010, 0111, 1000, 1001, 1010, 1011,1101, 1110,1111 are reserved.
For details see
For details see
For details see
Transmitter Holding Register”
Symbol
FIFOEN
RXFIFO
RES
TXFIFO
RES
DMAMO
DE
-
0x400C 1008 (UART2), 0x400C 2008 (UART3)) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
Section 32.5.8 “UART Line Status Register”
Section 32.5.1 “UART Receiver Buffer Register”
Section 32.5.5 “UART Interrupt Identification Register”
Rev. 00.13 — 20 July 2011
FIFO Enable.
UART FIFOs are disabled. Must not be used in the application.
Active high enable for both UART Rx and TX FIFOs and FCR[7:1]
access. This bit must be set for proper UART operation. Any
transition on this bit will automatically clear the UART FIFOs.
RX FIFO Reset.
No impact on either of UART FIFOs.
Writing a logic 1 to FCR[1] will clear all bytes in UART Rx FIFO,
reset the pointer logic. This bit is self-clearing.
TX FIFO Reset.
No impact on either of UART FIFOs.
Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO,
reset the pointer logic. This bit is self-clearing.
DMA Mode Select. When the FIFO enable bit (bit 0 of this
register) is set, this bit selects the DMA mode.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 32: LPC18xx USART0_2_3
and
Section 32.5.2 “UART
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
NA