LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 856

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 800. Register overview: I
[1]
Table 801. Register overview: I
<Document ID>
User manual
Name
MMCTRL
ADR1
ADR2
ADR3
DATA_BUFFE
R
MASK0
MASK1
MASK2
MASK3
Name
CONSET
STAT
IDAT
ADR0
SCLH
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Access Address
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
Access Address
R/W
RO
R/W
R/W
R/W
R/W
offset
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
offset
0x000
0x004
0x008
0x00C
0x010
2
2
C0 (base address 0x400A 1000)
C1 (base address 0x400E 0000)
Description
Monitor mode control register.
I2C Slave Address Register 1. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
I2C Slave Address Register 2. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
I2C Slave Address Register 3. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
Data buffer register. The contents of the 8 MSBs of the DAT shift register
will be transferred to the DATA_BUFFER automatically after every nine
bits (8 bits of data plus ACK or NACK) has been received on the bus.
I2C Slave address mask register 0 . This mask register is associated
with ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 1 . This mask register is associated
with ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 2 . This mask register is associated
with ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 3 . This mask register is associated
with ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
Description
I2C Control Set Register. When a one is written to a bit of this register,
the corresponding bit in the I
no effect on the corresponding bit in the I
I2C Status Register. During I
status codes that allow software to determine the next action needed.
I2C Data Register. During master or slave transmit mode, data to be
transmitted is written to this register. During master or slave receive
mode, data that has been received may be read from this register.
I2C Slave Address Register 0. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
SCH Duty Cycle Register High Half Word. Determines the high time of
the I
All information provided in this document is subject to legal disclaimers.
2
C clock.
Rev. 00.13 — 20 July 2011
2
2
2
2
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
2
…continued
C control register is set. Writing a zero has
2
C operation, this register provides detailed
Chapter 37: LPC18xx I2C-bus interface
2
C control register.
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reset
value
0x00
0xF8
0x00
0x00
0x04
[1]
[1]