LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 728

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.12.1 Baud rate calculation
Table 678. UART Fractional Divider Register (FDR - addresses 0x4008 1028 (UART0), 0x400C
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART disabled making sure that UART is
fully software and hardware compatible with UARTs not equipped with this feature.
The UART baud rate can be calculated as:
Where UART_PCLK is the peripheral clock, DLM and DLL are the standard UART baud
rate divider registers, and DIVADDVAL and MULVAL are UART fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of the FDR should not be modified while transmitting/receiving data or data may
be lost or corrupted.
If the FDR register value does not comply to these two requests, then the fractional divider
output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the
clock will not be divided.
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baud rate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
Bit
3:0
7:4
31:8 -
1. 1  MULVAL  15
2. 0  DIVADDVAL  14
3. DIVADDVAL< MULVAL
Function
DIVADDVAL
MULVAL
1028 (UART2), 0x400C 2028 (UART3)) bit description
UART
All information provided in this document is subject to legal disclaimers.
Description
Baud rate generation pre-scaler divisor value.
If this field is 0, fractional baud rate generator will not impact the
UART baud rate.
Baud rate pre-scaler multiplier value.
This field must be greater or equal 1 for UART to operate
properly, regardless of whether the fractional baud rate
generator is used or not.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
baudrate
Rev. 00.13 — 20 July 2011
=
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16


256

DLM
+
PCLK
DLL
Chapter 32: LPC18xx USART0_2_3




1
+
DivAddVal
---------------------------- -
MulVal
UM10430
© NXP B.V. 2011. All rights reserved.


Reset
value
0
1
0
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