LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 735

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 685. UART Synchronous mode control registers (SYNCCTRL - address addresses
After reset, synchronous mode is disabled. Synchronous mode allows the user to send
(synchronous master mode) or receive (synchronous slave mode) a clock with the serial
input and output data. Synchronous mode is enabled by setting the SYNC bit. The CSRC
bit can be used to switch between synchronous slave mode (logic 0) and synchronous
master mode (logic 1). The serial data can either be sampled on the rising edge (default)
or the falling edge of the serial clock. When the STARTSTOPDISABLE bit is set, the FES
bit is hardware overwritten to sample on the falling edge.
A master clock is only required to generate a clock when transmitting data. In this case,
data can only be received when data is transmitted. When the CSCEN bit is set, the clock
will always be running (during synchronous master mode only), allowing data to be
received continuously.
Note that this option should not be used in combination with STARTSTOPDISABLE
(during full-duplex communication). The continuous clock can be automatically stopped by
hardware after having received a complete character. This can be done by asserting the
CCCLR bit. This is useful in half-duplex mode, where the clock cannot be generated by
sending a character. After the reception of one character, the CSCEN bit is automatically
cleared by hardware. When another character needs to be received, the CSCEN should
be enabled again.
By default data transmission and reception performs the same in asynchronous mode and
synchronous mode. When the STARTSTOPDISABLE bit is set, no start and stop bits are
transmitted (nor are they received). This means that all bits that are send or received (a
clock is running) are data bits.
Remark: The value of the SYNCCTRL register should not be modified while
transmitting/receiving, data or data might get lost or corrupted.
Remark: The SYNCCTRL register should not be enabled in combination with the
SCICTRL register, as only asynchronous smart card is supported.
Bit
5
6
31:7
Symbol
SSSDIS
CCCLR
-
0x4008 1058 (UART0), 0x400C 1058 (UART2), 0x400C 2058 (UART3)) bit
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0
1
0
1
Description
Start/stop bits
Send start and stop bits as in other modes.
Do not send start/stop bits.
Continuous clock clear
CSCEN is under software control.
Hardware clears CSCEN after each character is
received.
Reserved. The value read from a reserved bit is not
defined.
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
NA