LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 633

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
25.8 Example timer operation
25.9 Architecture
<Document ID>
User manual
Fig 70. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.
Fig 71. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled
prescale counter
timer counter
(counter enable)
timer counter
prescale
interrupt
counter
counter
PCLK
timer
reset
interrupt
TCR[0]
PCLK
Figure 70
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 71
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure
4
2
4
2
72.
shows a timer configured to reset the count and generate an interrupt on match.
shows a timer configured to stop and generate an interrupt on match. The
0
0
All information provided in this document is subject to legal disclaimers.
1
5
1
5
1
Rev. 00.13 — 20 July 2011
2
2
0
0
1
6
6
0
2
0
Chapter 25: LPC18xx Timer0/1/2/3
1
0
2
0
UM10430
1
© NXP B.V. 2011. All rights reserved.
1
633 of 1164