LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 632

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
25.7.12 DMA operation
Table 545. Timer count control register CTCR(CTCR - addresses 0x4008 4070 (TIMER0),
DMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits of
each timer. In order to have an effect, the GPDMA must be configured and the relevant
timer DMA request selected as a DMA source via the CREG block, see
When a timer is initially set up to generate a DMA request, the request may already be
asserted before a match condition occurs. An initial DMA request may be avoided by
having software by write a one to the interrupt flag location, as if clearing a timer interrupt.
See
the GPDMA controller.
Bit
1:0
3:2
31:4
Section
Symbol
CTMODE
CINSEL
-
0x4008 5070 (TIMER1), 0x400C 3070 (TIMER2), 0x400C 4070 (TIMER3)) bit
description
25.7.1. A DMA request will be cleared automatically when it is acted upon by
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
-
Rev. 00.13 — 20 July 2011
Description
Counter/Timer Mode
This field selects which rising PCLK edges can increment
Timer’s Prescale Counter (PC), or clear PC and increment
Timer Counter (TC).
Timer Mode: the TC is incremented when the Prescale
Counter matches the Prescale Register.
Timer Mode: every rising PCLK edge
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on both edges on the
CAP input selected by bits 3:2.
Count Input Select
When bits 1:0 in this register are not 00, these bits select
which CAP pin is sampled for clocking:
CAPn.0 for TIMERn
CAPn.1 for TIMERn
CAPn.2 for TIMERn
CAPn.3 for TIMERn
Note: If Counter mode is selected for a particular CAPn
input in the TnCTCR, the 3 bits for that input in the Capture
Control Register (TnCCR) must be programmed as 000.
However, capture and/or interrupt can be selected for the
other 3 CAPn inputs in the same timer.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 25: LPC18xx Timer0/1/2/3
UM10430
© NXP B.V. 2011. All rights reserved.
Table
35.
632 of 1164
Reset
value
00
00
NA