LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 723

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.10 UART Auto-baud Control Register
32.5.9 UART Scratch Pad Register
Table 673. UART Line Status Register Read Only (LSR - addresses 0x4008 1014 (UART0),
The SCR has no effect on the UART operation. This register can be written and/or read at
user’s discretion. There is no provision in the interrupt interface that would indicate to the
host that a read or write of the SCR has occurred.
Table 674. UART Scratch Pad Register (SCR - addresses 0x4008 101C (UART0), 0x400C
The UART Auto-baud Control Register (ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Table 675. Autobaud Control Register (ACR - addresses 0x4008 1020 (UART0), 0x400C 1020
Bit Symbol
7
8
31:
9
Bit
7:0
31:8
Bit
0
1
-
RXFE
TXERR
Symbol
START
MODE
Symbol Description
PAD
-
0x400C 1014 (UART2), 0x400C 2014 (UART3) ) bit description
101C (UART2), 0x400C 201C (UART3)) bit description
(UART2), 0x400C 2020 (UART3)) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
-
Scratch pad. A readable, writable byte.
Reserved
0
1
0
1
Rev. 00.13 — 20 July 2011
Error in RX FIFO.
LSR[7] is set when a character with a RX error such as framing
error, parity error or break interrupt, is loaded into the RBR. This
bit is cleared when the LSR register is read and there are no
subsequent errors in the UART FIFO.
RBR contains no UART RX errors or FCR[0]=0.
UART RBR contains at least one UART RX error.
Error in transmitted character.
A NACK response is given by the receiver in Smart card T=0
mode. This bit is cleared when the LSR register is read.
No error (normal default condition).
A NACK response is received during Smart card T=0 operation.
Reserved
Value Description
0
1
0
1
Start bit.
This bit is automatically cleared after auto-baud
completion.
Auto-baud stop (auto-baud is not running).
Auto-baud start (auto-baud is running). Auto-baud run
bit. This bit is automatically cleared after auto-baud
completion.
Auto-baud mode select bit.
Mode 0.
Mode 1.
Chapter 32: LPC18xx USART0_2_3
UM10430
…continued
© NXP B.V. 2011. All rights reserved.
Reset Value
0x00
-
723 of 1164
Reset
value
0
0
Reset
Value
0
0
-