LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 557

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.6.14 Color Palette registers
23.6.15 Cursor Image registers
The PAL register contain 256 palette entries organized as 128 locations of two entries per
word.
Each word location contains two palette entries. This means that 128 word locations are
used for the palette. When configured for little-endian byte ordering, bits [15:0] are the
lower numbered palette entry and [31:16] are the higher numbered palette entry. When
configured for big-endian byte ordering this is reversed, because bits [31:16] are the low
numbered palette entry and [15:0] are the high numbered entry.
Note: Only TFT displays use all of the palette entry bits.
The contents of the PAL register are described in
Table 469. Color Palette registers (PAL, address 0x4000 8200 (PAL0) to 0x4000 83FC
The CRSR_IMG register area contains 256-word wide values which are used to define
the image or images overlaid on the display by the hardware cursor mechanism. The
image must always be stored in LBBP mode (little-endian byte, big-endian pixel) mode, as
described in
each pixel in the cursor.
Depending on the state of bit 0 in the CRSR_CFG register (see Cursor Configuration
register description), the cursor image RAM contains either four 32x32 cursor images, or
a single 64x64 cursor image.
Bits
4:0
9:5
14:10
15
20:16
25:21
30:26
31
Function
R04_0
G04_0
B04_0
I0
R14_0
G14_0
B14_0
I1
(PAL255)) bit description
Section
All information provided in this document is subject to legal disclaimers.
23.7.5.6. Two bits are used to encode color and transparency for
Rev. 00.13 — 20 July 2011
Description
Red palette data.
For STN displays, only the four MSBs, bits [4:1], are used. For
monochrome displays only the red palette data is used. All of the
palette registers have the same bit fields.
Green palette data.
Blue palette data.
Intensity / unused bit.
Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT
display, doubling the number of colors to 64K, where each color
has two different intensities.
Red palette data.
For STN displays, only the four MSBs, bits [4:1], are used. For
monochrome displays only the red palette data is used. All of the
palette registers have the same bit fields.
Green palette data.
Blue palette data.
Intensity / unused bit.
Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT
display, doubling the number of colors to 64K, where each color
has two different intensities.
Table
469.
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
557 of 1164
Reset
value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0