LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1106

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Loop-back mode combined with Silent mode:
mode and Silent mode by programming bits LBACK and SILENT to one at the same time.
This mode can be used for a “Hot Selftest”, meaning the C_CAN can be tested without
affecting a running CAN system connected to the pins CAN_TXD and CAN_RXD. In this
mode the CAN_RXD pin is disconnected from the CAN Core and the CAN_TXD pin is
held recessive.
Basic mode:
bit BASIC to one. In this mode the CAN controller runs without the Message RAM.
The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the
IF1 Registers is requested by writing the BUSY bit of the IF1 Command Request Register
to ‘1’. The IF1 Registers are locked while the BUSY bit is set. The BUSY bit indicates that
the transmission is pending.
As soon the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN
Core and the transmission is started. When the transmission has completed, the BUSY bit
is reset and the locked IF1 Registers are released.
A pending transmission can be aborted at any time by resetting the BUSY bit in the IF1
Command Request Register while the IF1 Registers are locked. If the CPU has reset the
BUSY bit, a possible retransmission in case of lost arbitration or in case of an error is
disabled.
Fig 173. CAN core in Loop-back mode
Fig 174. CAN core in Loop-back mode combined with Silent mode
The CAN Core can be set in Basic mode by programming the Test Register
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
C_CAN
C_CAN
TD0, TD1 RD0, RD1
TD0, TD1 RD0, RD1
= 1
Rx
Rx
CAN CORE
CAN CORE
It is also possible to combine Loop-back
Tx
Tx
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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