LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 281

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 215. DMA Channel Configuration registers (CCONFIG, 0x4000 2110 (C0CONFIG) to 0x4000 21F0 (C7CONFIG))
<Document ID>
User manual
Bit
17
18
31:19 -
Symbol
A
H
16.6.20.1 Lock control
16.6.20.2 Flow control and transfer type
bit description
The lock control may set the lock bit by writing a 1 to bit 16 of the CCONFIG Register.
When a burst occurs, the AHB arbiter will not de-grant the master during the burst until the
lock is deasserted. The DMA Controller can be locked for a a single burst such as a long
source fetch burst or a long destination drain burst. The DMA Controller does not usually
assert the lock continuously for a source fetch burst followed by a destination drain burst.
There are situations when the DMA Controller asserts the lock for source transfers
followed by destination transfers. This is possible when internal conditions in the DMA
Controller permit it to perform a source fetch followed by a destination drain back-to-back.
Table 216
Table
Table 216. Flow control and transfer type bits
Bit value
000
001
010
011
100
101
110
111
…continued
Value
0
1
Table
lists the bit values of the three flow control and transfer type bits identified in
215.
Description
Active:
0 = there is no data in the FIFO of the channel.
1 = the channel FIFO has data.
This value can be used with the Halt and Channel Enable bits to
cleanly disable a DMA channel. This is a read-only bit.
Halt:
0 = enable DMA requests.
1 = ignore further source DMA requests.
The contents of the channel FIFO are drained.
This value can be used with the Active and Channel Enable bits
to cleanly disable a DMA channel.
Enable DMA requests.
Ignore further source DMA requests.
Reserved, do not modify, masked on read.
Transfer type
Memory to memory
Memory to peripheral
Peripheral to memory
Source peripheral to destination peripheral
Source peripheral to destination peripheral
Memory to peripheral
Peripheral to memory
Source peripheral to destination peripheral
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Controller
DMA
DMA
DMA
DMA
Destination peripheral
Peripheral
Peripheral
Source peripheral
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
281 of 1164
Access
RO
R/W
-