LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 347

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.8.2.1 Memory transaction endianness
19.8.2.2 Memory transaction size
19.8.2.3 Write protected memory areas
19.8.4.1 Write buffers
19.8.2 AHB slave memory interface
19.8.3 Pad interface
19.8.4 Data buffers
Note: If an access is attempted with a size other than a word (32 bits), it causes an
ERROR response to the AHB bus and the transfer is terminated.
The AHB slave memory interface allows access to external memories.
The endianness of the data transfers to and from the external memories is determined by
the Endian mode (N) bit in the Config register.
Note: The memory controller must be idle (see the busy field of the Status Register)
before endianness is changed, so that the data is transferred correctly.
Memory transactions can be 8, 16, or 32 bits wide. Any access attempted with a size
greater than a word (32 bits) causes an ERROR response to the AHB bus and the transfer
is terminated.
Write transactions to write-protected memory areas generate an ERROR response to the
AHB bus and the transfer is terminated.
The pad interface block provides the interface to the pads. The pad interface uses one
feedback clock per lane, FBCLKIN[3:0], from the CLKOUT[3:0] outputs of the EMC to
resynchronize SDRAM read data from the off-chip to on-chip domains.
The EMC dynamic memory requires 2 CLKOUT signals for 16-bit memory and 4 CLKOUT
signals for 32-bit memory.
The AHB interface reads and writes via buffers to improve memory bandwidth and reduce
transaction latency. The EMC contains four 16-word buffers. The buffers can be used as
read buffers, write buffers, or a combination of both. The buffers are allocated
automatically.
The buffers must be disabled during SDRAM and SyncFlash initialization. They must also
be disabled when performing SyncFlash commands. The buffers must be enabled during
normal operation.
The buffers can be enabled or disabled for static memory using the StaticConfig
Registers.
Write buffers are used to:
•
Merge write transactions so that the number of external transactions are minimized.
Buffer data until the EMC can complete the write transaction, improving AHB write
latency.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
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