LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1071

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 1003.I2S Receive Clock Rate register (RXRATE - address 0x400A 2024) bit description
Table 1004.I2S Transmit Clock Rate register (TXBITRATE - address 0x400A 2028) bit description
<Document ID>
User manual
Bit
7:0
15:8
31:16
Bit
5:0
31:6
Symbol
Y_DIVIDER
X_DIVIDER
-
Symbol
TX_BITRATE
-
42.9.6.10 I2S Receive Clock Rate register
42.9.6.12 I2S Receive Clock Bit Rate register
42.9.6.11 I2S Transmit Clock Bit Rate register
Description
I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the
receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of
0 stops the clock.
I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the
receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide
range of possibilities. Note: the resulting ratio X/Y is divided by 2.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
with the jitter. The frequency averages out to exactly (7/17) / 2, but some clocks will be a
slightly different length than their neighbors. It is possible to avoid jitter entirely by
choosing fractions such that X divides evenly into Y, such as 2/4, 2/6, 3/9, 1/N, etc.
The MCLK rate for the I2S receiver is determined by the values in the RXRATE register.
The required RXRATE setting depends on the peripheral clock rate (PCLK_I2S =
CLK_APB1_I2S) and the desired MCLK rate (such as 256 fs).
The receiver MCLK rate is generated using a fractional rate generator, dividing down the
frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be
chosen to produce a frequency twice that desired for the receiver MCLK, which must be
an integer multiple of the receiver bit clock rate. Fractional rate generators have some
aspects that the user should be aware of when choosing settings. These are discussed in
Section
I2SRXMCLK = PCLK_I2S * (X/Y) /2
Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
greater than or equal to X.
The bit rate for the I2S transmitter is determined by the value of the TXBITRATE register.
The value depends on the audio sample rate desired, and the data size and format
(stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data requires a
bit rate of 48,000´16´2 = 1.536 MHz.
The bit rate for the I2S receiver is determined by the value of the RXBITRATE register.
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for RXBITRATE.
Description
I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the
transmit bit clock.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
42.9.6.9.1. The equation for the fractional rate generator is:
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
1071 of 1164
Reset
value
0
0
-
Reset
value
0
-