LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 522

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.8.2.3 Transmit frame processing
22.8.2.4 Transmit polling suspended
The Transmit DMA expects that the data buffers contain complete Ethernet frames,
excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain
valid data. If the Transmit Descriptor indicates that the MAC core must disable CRC or
PAD insertion, the buffer must have complete Ethernet frames (excluding preamble),
including the CRC bytes.
Frames can be data-chained and can span several buffers. Frames must be delimited by
the First Descriptor (TDES1[29]) and the Last Descriptor (TDES1[30]), respectively.
As transmission starts, the First Descriptor must have (TDES1[29]) set. When this occurs,
frame data transfers from the Host buffer to the MTL Transmit FIFO. Concurrently, if the
current frame has the Last Descriptor (TDES1[30]) clear, the Transmit Process attempts
to acquire the Next Descriptor. The Transmit Process expects this descriptor to have
TDES1[29] clear. If TDES1[30] is clear, it indicates an intermediary buffer. If TDES1[30] is
set, it indicates the last buffer of the frame.
After the last buffer of the frame has been transmitted, the DMA writes back the final
status information to the Transmit Descriptor 0 (TDES0) word of the descriptor that has
the last segment set in Transmit Descriptor 1 (TDES1[30]). At this time, if Interrupt on
Completion (TDES1[31]) was set, Transmit Interrupt (DMA Status register, bit 0) is set, the
Next Descriptor is fetched, and the process repeats.
The actual frame transmission begins after the MTL Transmit FIFO has reached either a
programmable transmit threshold (DMA Operation Mode register, bits [16:14]), or a full
frame is contained in the FIFO. There is also an option for Store and Forward Mode (DMA
Operation Mode register, bit [21]). Descriptors are released (Own bit TDES0[31] clears)
when the DMA finishes transferring the frame.
Remark: To ensure proper transmission of a frame and the next frame, you must specify
a non-zero buffer size for the transmit descriptor that has the Last Descriptor (TDES1[30])
set.
Transmit polling can be suspended by either of the following conditions:
If the second condition occur, both Abnormal Interrupt Summary (DMA Status register
Table
information is written to Transmit Descriptor 0, causing the suspension. If the DMA goes
into SUSPEND state because of the first condition, then both Normal Interrupt Summary
(DMA Status register
Table
In both cases, the position in the Transmit List is retained. The retained position is that of
the descriptor following the Last Descriptor closed by the DMA.
•
•
The DMA detects a descriptor owned by the Host (TDES0[31]=0). To resume, the
driver must give descriptor ownership to the DMA and then issue a Poll Demand
command.
A frame transmission is aborted when a transmit error because of underflow is
detected. The appropriate Transmit Descriptor 0 (TDES0) bit is set.
427) and Transmit Underflow bits (DMA Status register
427) are set.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 00.13 — 20 July 2011
427) and Transmit Buffer Unavailable (DMA Status register
Chapter 22: LPC18xx Ethernet
Table
427) are set, and the
UM10430
© NXP B.V. 2011. All rights reserved.
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