LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 263

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

16.1 How to read this chapter
16.2 Basic configuration
16.3 Features
<Document ID>
User manual
The GPDMA is available on all LPC18xx parts.
See
The GPDMA is configured as follows:
Table 194. GPDMA clocking and power control
GPDMA
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UM10430
Chapter 16: LPC18xx General Purpose DMA (GPDMA)
controller
Rev. 00.13 — 20 July 2011
See
The GPDMA is reset by the DMA_RST (reset # 19).
The DMAMUX register in the CREG block (see
peripherals for each GPDMA-to-peripheral line.
Eight DMA channels. Each channel can support an unidirectional transfer.
16 DMA request lines.
Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority.
AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
Two AHB bus masters for transferring data. These interfaces transfer data when a
DMA request goes active. Master 1 can access memories and peripherals, master 0
can access memories only.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
Internal four-word FIFO per channel.
Table 921
Table 194
for the DMA-to-peripheral connections for parts LPC1850/30/20/10 Rev ‘-’.
Base clock
BASE_M3_CLK
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
CLK_M3_DMA
Branch clock
Table
35) selects between up to three
Maximum frequency
150 MHz
© NXP B.V. 2011. All rights reserved.
User manual
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