LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 518

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.8.2.1 TxDMA operation: Default (non-OSF) mode
22.8.2 Transmission
When round-robin arbitration is selected (DA bit of Register
Register) is reset), the arbiter allocates the data bus in the ratio set by the PR bits of DMA
Register
simultaneously. When the DA bit is set, the Receive DMA always gets priority over the
Transmit DMA for data access by default. When the TXPR bit (bit 27 of DMA register
Table
The transmit DMA engine in default mode proceeds as follows:
The TxDMA transmission flow in default mode is shown in
1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit
2. Once the ST bit (DMA Register) is set, the DMA enters the Run state.
3. While in the Run state, the DMA polls the Transmit Descriptor list for frames requiring
4. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA
5. The DMA fetches the Transmit data from the Host memory and transfers the data to
6. If an Ethernet frame is stored over data buffers in multiple descriptors, the DMA
7. When frame transmission is complete, if IEEE 1588 time stamping was enabled for
8. Transmit Interrupt (DMA Register
9. In the Suspend state, the DMA tries to re-acquire the descriptor (and thereby return to
(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet Frame
data.
transmission. After polling starts, it continues in either sequential descriptor ring order
or chained order. If the DMA detects a descriptor flagged as owned by the Host, or if
an error condition occurs, transmission is suspended and both the Transmit Buffer
Unavailable (DMA Register
Table
decodes the Transmit Data Buffer address from the acquired descriptor.
the MTL for transmission.
closes the intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5
are repeated until the end-of-Ethernet-frame data is transferred to the MTL.
the frame (as indicated in the transmit status) the timestamp value obtained from MTL
is written to the transmit descriptor (TDES2 and TDES3) that contains the
end-of-frame buffer. The status information is then written to this transmit descriptor
(TDES0). Because the Own bit is cleared during this step, the Host now owns this
descriptor. If time stamping was not enabled for this frame, the DMA does not alter the
contents of TDES2 and TDES3.
frame that has Interrupt on Completion (TDES1[31]) set in its Last Descriptor. The
DMA engine then returns to Step 3.
Step 3) when it receives a Transmit Poll demand and the Underflow Interrupt Status
bit is cleared.
421) is also set, then the Transmit DMA gets priority over the Receive DMA as .
Table
427) bits are set. The Transmit Engine proceeds to Step 9.
421, when both Transmit and Receive DMAs are requesting for access
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table
427) and Normal Interrupt Summary (DMA Register
Table
427) is set after completing transmission of a
Chapter 22: LPC18xx Ethernet
Figure
Table 421
47.
UM10430
(Bus Mode
© NXP B.V. 2011. All rights reserved.
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