LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 445

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 368. USB Command register in host mode (USBCMD_H - address 0x4000 7140) bit description
<Document ID>
User manual
Bit
4
5
6
7
9:8
10
11
12
13
14
Symbol
PSE
ASE
IAA
-
ASP1_0
-
ASPE
-
-
-
Value
0
1
0
1
0
1
-
-
0
1
-
-
-
Description
This bit controls whether the host controller skips processing the
periodic schedule.
Do not process the periodic schedule.
Use the PERIODICLISTBASE register to access the periodic
schedule.
This bit controls whether the host controller skips processing the
asynchronous schedule.
Do not process the asynchronous schedule.
Use the ASYNCLISTADDR to access the asynchronous schedule.
This bit is used as a doorbell by software to tell the host controller to
issue an interrupt the next time it advances asynchronous schedule.
The host controller sets this bit to zero after it has set the Interrupt on
Sync Advance status bit in the USBSTS register to one.
Software must write a 1 to this bit to ring the doorbell.
When the host controller has evicted all appropriate cached schedule
states, it sets the Interrupt on Async Advance status bit in the
USBSTS register. If the Interrupt on Sync Advance Enable bit in the
USBINTR register is one, then the host controller will assert an
interrupt at the next interrupt threshold.
Software should not write a one to this bit when the asynchronous
schedule is inactive. Doing so will yield undefined results.
Reserved
Asynchronous schedule park mode.
Contains a count of the number of successive transactions the host
controller is allowed to execute from a high-speed queue head on the
Asynchronous schedule before continuing traversal of the
Asynchronous schedule. Valid values are 0x1 to 0x3.
Remark: Software must not write 00 to this bit when Park Mode
Enable is one as this will result in undefined behavior.
Reserved.
Asynchronous Schedule Park Mode Enable
Park mode is disabled.
Park mode is enabled.
Reserved.
Not used in Host mode.
Reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
11
0
1
0
0
…continued
445 of 1164
Access
R/W
R/W
R/W
R/W
-
-
-
-
R/W