LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1154

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
21.6.16.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 470
21.6.17
21.6.18
21.6.19
Chapter 22: LPC18xx Ethernet
22.1
22.2
22.3
22.4
22.5
22.6
22.6.1
22.6.2
22.6.3
22.6.4
22.6.5
22.6.6
22.6.7
22.6.8
22.6.9
22.6.10
22.6.11
22.6.12
22.6.13
22.6.14
22.6.15
22.6.16
22.6.17
22.6.18
22.6.19
22.6.20
22.6.21
22.6.22
22.6.23
22.6.24
22.6.25
22.6.26
22.6.27
22.6.28
Chapter 23: LPC18xx LCD
23.1
23.2
23.3
23.4
23.4.1
<Document ID>
User manual
How to read this chapter . . . . . . . . . . . . . . . . 478
Basic configuration . . . . . . . . . . . . . . . . . . . . 478
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
General description . . . . . . . . . . . . . . . . . . . . 479
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 479
Register description . . . . . . . . . . . . . . . . . . . 480
How to read this chapter . . . . . . . . . . . . . . . . 540
Basic configuration . . . . . . . . . . . . . . . . . . . . 540
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
General description . . . . . . . . . . . . . . . . . . . . 541
USB Endpoint Setup Status register
(ENDPSETUPSTAT). . . . . . . . . . . . . . . . . . . 471
USB Endpoint Prime register (ENDPTPRIME). . .
471
USB Endpoint Flush register (ENDPTFLUSH) . . .
472
MAC Configuration register . . . . . . . . . . . . . 481
MAC Frame filter register . . . . . . . . . . . . . . . 484
MAC Hash table high register. . . . . . . . . . . . 485
MAC Hash table . . . . . . . . . . . . . low register 486
MAC MII Address register. . . . . . . . . . . . . . . 486
MAC MII Data register . . . . . . . . . . . . . . . . . 488
MAC Flow control register . . . . . . . . . . . . . . 488
MAC VLAN tag register . . . . . . . . . . . . . . . . 490
MAC Debug register . . . . . . . . . . . . . . . . . . . 490
MAC Remote wake-up frame filter register. . 491
MAC PMT control and status register. . . . . . 492
MAC Interrupt status register . . . . . . . . . . . . 492
MAC Interrupt mask register. . . . . . . . . . . . . 493
MAC Address 0 high register . . . . . . . . . . . . 493
MAC Address 0 low register . . . . . . . . . . . . . 493
MAC IEEE1588 time stamp control register . 494
DMA Bus mode register . . . . . . . . . . . . . . . . 496
DMA Transmit poll demand register . . . . . . . 498
DMA Receive poll demand register . . . . . . . 499
DMA Receive descriptor list address register 499
DMA Transmit descriptor list address register 499
DMA Status register . . . . . . . . . . . . . . . . . . . 500
DMA Operation mode register . . . . . . . . . . . 502
DMA Interrupt enable register . . . . . . . . . . . 505
DMA Missed frame and buffer overflow counter
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
DMA Receive interrupt watchdog timer register . .
508
DMA Current host transmit descriptor register . . .
508
DMA Current host receive descriptor register 509
Programmable parameters . . . . . . . . . . . . . . 541
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
21.6.20
21.6.21
21.6.22
21.6.23
21.7
22.6.29
22.6.30
22.7
22.7.1
22.7.1.1
22.7.1.2
22.7.1.3
22.7.1.4
22.7.2
22.7.3
22.8
22.8.1
22.8.1.1
22.8.1.2
22.8.1.3
22.8.1.4
22.8.2
22.8.2.1
22.8.2.2
22.8.2.3
22.8.2.4
22.8.2.5
22.8.2.6
22.8.2.7
22.8.2.8
22.8.2.9
22.8.2.10 Error response to DMA . . . . . . . . . . . . . . . . 527
22.9
22.9.1
22.9.2
23.4.2
23.4.3
23.4.3.1
23.4.3.2
23.4.3.3
23.5
Functional description . . . . . . . . . . . . . . . . . 477
Functional description . . . . . . . . . . . . . . . . . 509
DMA controller description . . . . . . . . . . . . . 514
Ethernet descriptors (enhanced format). . . 527
Pin description . . . . . . . . . . . . . . . . . . . . . . . 543
USB Endpoint Status register (ENDPTSTAT) 473
USB Endpoint Complete register
(ENDPTCOMPLETE). . . . . . . . . . . . . . . . . . 473
USB Endpoint 0 Control register (ENDPTCTRL0)
474
Endpoint 1 to 3 control registers . . . . . . . . . 475
DMA Current host transmit buffer address register
509
DMA Current host receive buffer address register
509
Power management block . . . . . . . . . . . . . . 510
Remote wake-up frame registers. . . . . . . . . 510
Filter i byte mask . . . . . . . . . . . . . . . . . . . . . . 510
Filter i command . . . . . . . . . . . . . . . . . . . . . . 511
Filter i offset . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Filter i CRC-16 . . . . . . . . . . . . . . . . . . . . . . . . 511
Remote wake-up detection . . . . . . . . . . . . . . 511
Magic packet detection . . . . . . . . . . . . . . . . 512
System considerations during power-down . 512
DMA arbiter functions . . . . . . . . . . . . . . . . . 513
IPC Receive checksum offload engine . . . . 514
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 515
Host bus burst access . . . . . . . . . . . . . . . . . 516
Host data buffer alignment . . . . . . . . . . . . . . 516
Example: Buffer read . . . . . . . . . . . . . . . . . . . 517
Example: Buffer write. . . . . . . . . . . . . . . . . . . 517
Buffer size calculations . . . . . . . . . . . . . . . . 517
DMA arbiter for MAC-DMA and MAC-AHB cores
517
Transmission . . . . . . . . . . . . . . . . . . . . . . . . 518
TxDMA operation: Default (non-OSF) mode 518
TxDMA operation: OSF mode . . . . . . . . . . . 519
Transmit frame processing. . . . . . . . . . . . . . 522
Transmit polling suspended . . . . . . . . . . . . . 522
Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Receive descriptor acquisition . . . . . . . . . . . 525
Receive frame processing . . . . . . . . . . . . . . 525
Receive process suspended . . . . . . . . . . . . 526
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Transmit descriptor . . . . . . . . . . . . . . . . . . . 527
Receive descriptor . . . . . . . . . . . . . . . . . . . . 533
Hardware cursor support . . . . . . . . . . . . . . . 541
Types of LCD panels supported. . . . . . . . . . 542
TFT panels. . . . . . . . . . . . . . . . . . . . . . . . . . 542
Color STN panels. . . . . . . . . . . . . . . . . . . . . 542
Monochrome STN panels . . . . . . . . . . . . . . 542
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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